Error in line 3 syntax error

[devesh kadambari]

module de_3_to_8( in,decoder_out);

  input [3:0] in;

  output [7:0] decoder_out;// Error in syntax

  //individual wires

  assign decoder_out[0]= ~in[2] & ~in[1] & ~in[0];

  assign decoder_out[1]= ~in[2] & ~in[1] & in[0];

  assign decoder_out[2]= ~in[2] & in[1] & ~in[0]; 

  assign decoder_out[3]= ~in[2] & in[1] & in[0];

  assign decoder_out[4]= in[2] & ~in[1] & ~in[0];

  assign decoder_out[5]= in[2] & ~in[1] &  in[0];

  assign decoder_out[6]= in[2] &  in[1] & ~in[0];

  assign decoder_out[7]= in[2] &  in[1] &  in[0];

 

endmodule

I`m getting an error at the output declaration shown above. I`m not understanding how is the syntax wrong in line 3. Help needed

[ambar noatay]

Hey  this code is working on Icarus Verilog 0.9.7 . 

[EDA Playground]

I see no errors. Neither does Riviera Pro. BTW, it is much easier just to post the URL of your code than to cut and paste it.

Matthew

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