Mixed Language simulation in EDA playgrounf

[SriGanesh DuraiKannu]

Hello all

         How to do mixed language simulation in EDA playground?  My design is VHDL and TB is UVM. 

[Alexandru Dinu]

I think not. At least, I tried verilog-vhdl combination, and I did not succeed. This improvement of EDA Playground which consists in adding possibility to run a TB consisting in SV verification environment and VHDL DUT would be welcome.

[EDA Playground]

Here's an example of mixed-language simulation using Xcelium:  https://www.edaplayground.com/x/4Zrj

[Alexandru Dinu]

Great! Thank you. I really need it!