Regarding multiple file run

[Ankit Singhal]

I have created two tabs in testbench and when I am running it then it is executing testbench.sv. How do I run test1.sv? how does simulator know which file to run?

[EDA Playground]

You need to use 

    `include

in either testbench.sv or design.sv

[Ankit Singhal]

what if I have to run only one file from those two?

[EDA Playground]

When (System)Verilog is selected, both files testbench.sv and design.sv are compiled. Any other tabs need to be included with `include. If there is nothing in one or both of testbench.sv and design.sv, that's fine.