VHDL code doubt

[Romildo Andrade]

Hello. I have a problem compiling the code, I don't know if I'm using the wrong integer for the "counter". I'm getting an error just for the counter, tell me if I'm on the right track please.

ELBWRITE ERROR ELBWRITE_0028: "The unresolved signal "counter" received values from multiple sources at 62 and 44 lines." "design.vhd" 62 0
COMP96 Compile failure 1 Errors 0 Warnings Analysis time : 10.0 [ms]

https://www.edaplayground.com/x/CQA_

[EDA Playground]

In VHDL you have special types called "resolved types". std_logic is one such type. Such types can be driven from more than one place (ie process or continuous assignment). If that happens then a special function (a so-called "resolution function") is called to calculate the value of the signal. So, for example, if one process is driving a '1' and another is driving a '0' on a std_logic signal then the value of that signal is 'X'. Another example: if one process is driving a '1' and another is driving a 'Z' on a std_logic signal then the value of that signal is '1'. Both these cases model what would happen with real electronics (and the resolution function is designed so that the std_logic type models real electronics). So, in the first case, if one lump of electronics is driving a 1 and another a 0, we have a short-circuit and this is represented by the 'X'. In the second case, if one lump of electronics is driving a 1 and another is high-impedance,  the lump driving the 1 wins and that is how you'd expect real electronics to behave.  

The VHDL integer type is not a resolved type. There is no resolution function. So, it is illegal to drive a signal of type integer from more than one process. (Think about it: it makes no sense to drive a signal of type integer from more than one process. If one process were driving a 5 and another were driving a 6, what value would you expect the INTEGER signal to have? 5.5? It makes no sense.)

So, that is the actual cause of your error. You are driving an unresolved type (integer) from more than one process - "Contador para manter o LED aceso por 4 us ou 12 us" and "Lógica de controle para a conversão de código Morse". 

However, you have a deeper, more fundamental problem. VHDL is a HARDWARE description language. You are designing hardware, not writing software. What hardware does you code represent? What circuit or block diagram would you draw based on your code? I think you need to draw out a circuit or block diagram first and then write your code. You should be using "templates":  . https://stackoverflow.com/questions/36539962/errorxst827-signal-count-cannot-be-synthesized-bad-synchronous-description/36543625#36543625 . 

When I say draw a diagram, I don't necessarily mean draw every logic gate. You can represent combinational logic as a cloud. But the diagram should show every flip-flop. If you draw such a diagram and then write your code, I think you will be a lot more successful. Sorry, but you need to scrap this code and start again. 

Do experienced VHDL engineers draw diagrams? Yes, frankly, we do. Not all the time, because we can think in the right way given our experience, but sometimes, yes - we do.