AND Logical gate simulation Test Bench

[Homero Daniel Rodriguez]

Hey guys, I am doing a test bench simulation for an AND Logical gate but it is not generating a result. I would really appreciate if you can help me out to find my mistake. Thank you 

//Design code

 `timescale 1ns / 1ps 

module Part_1( 

input wire Inp_1,

input wire Inp_2, 

output wire Outp 

); 

assign Outp = Inp_1 & Inp_2; 

endmodule 

///////////////////////////////////////////////////////////////////////////////////

//Code for Test Bench 

`timescale 1ns / 1ps 

module Part_1_Sim( 

 ); 

 

reg Inp_1_t; 

reg Inp_2_t; 

wire Outp_t; 

Part_1 UUT( 

 .Inp_1(Inp_1_t), 

 .Inp_2(Inp_2_t), 

 .Outp(Outp_t) 

 ); 

 initial 

 begin 

    Inp_1_t=1’b0; 

    Inp_2_t=1’b0; 

 end 

 always #5 Inp_1_t=~Inp_1_t; 

 always #10 Inp_2_t=~Inp_2_t; 

endmodule   

[mah...@gmail.com]

Here is the solution; 

https://www.edaplayground.com/x/g64

Please add timeout/simulation exit. 

[EDA Playground]

The easiest way to stop a simulation in Verilog is to add a call to $stop or $finish, eg line 28 of https://www.edaplayground.com/x/WNMc .

[Homero Daniel Rodriguez]

Thank you very much