How do I pass simple timing constraints to get timing report?

[Sungho Park]

I'm truly enjoying EDA playground tool!

I recently tried to synthesize my small design using mentor precision, to get a feel of size of logic and timing feedback. However, I do not get timing report due to missing constraint.

# Info: [12022]: Design has no timing constraint and no timing information. 

Can anyone help me to pass a very simple timing constraints, e.g. clock period?

Thanks,

Sungho 

[EDA Playground]

Here is an example of using Precision constraints. It's for VHDL, but should be equally applicable to (System)Verilog.

https://www.edaplayground.com/x/j3Ty

Matthew

[Sungho Park]

Thanks, it works!