systemverilog assertion on EPWave
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Billy Lin
May 14, 2024, 1:04:25 AM5/14/24
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Hi,
How can I have concurrent assertion "a2" on EPWave?
module top;
bit clk; //clock
always #5 clk = ~clk; //clock with period 10sec
bit sig1;
initial begin
repeat (2) begin
@(posedge clk);
end
sig1 = 1;
@(posedge clk);
sig1 = 0;
end
a2: assert property(@(posedge clk) sig1 |=> ~sig1);
initial begin
$dumpfile("dump.vcd"); $dumpvars;
#100;
$finish;
end
endmodule
How can I have concurrent assertion "a2" on EPWave?
As the example below, I only got bit signals such as clk and sig1
How can I see "a2"?
module top;
bit clk; //clock
always #5 clk = ~clk; //clock with period 10sec
bit sig1;
initial begin
repeat (2) begin
@(posedge clk);
end
sig1 = 1;
@(posedge clk);
sig1 = 0;
end
a2: assert property(@(posedge clk) sig1 |=> ~sig1);
initial begin
$dumpfile("dump.vcd"); $dumpvars;
#100;
$finish;
end
endmodule
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