Simulation error

[Surya Chatrati]

Hi,

I just joined the EDAplayground. Looks very interesting. I'd like to ask a couple of questions:

1. Is the license available only for 17 days? What after that?

2. I've written the design and testbench in VHDL, and on simulation, I get the following error:

   # VSIM: Error: Library `testbench' is either damaged or does not exist.

Finding VCD file...
No *.vcd file found. EPWave will not open. Did you use '$dumpfile("dump.vcd"); $dumpvars;'?

On googling, I've found a workaround, but that seems to be the solution for Verilog users. What is the analogous solution for VHDL users? Thank you.

[EDA Playground]

Hi Surya,

Sorry for the delay in replying. I have been on holiday.

Glad you're finding EDA Playground interesting...

1. The 17 days is the time left for the licence for VCS (it runs out at the end of the month). Hopefully, Synopsys will have very kindly updated the licence by then.

2. For Verilog you need to add "$dumpfile("dump.vcd"); $dumpvars;" to an initial block in your testbench. For VHDL, you don't need to worry - it is all handled automatically.

Matthew

[Joe Connolly]

Yes but what if you are using VHDL as your language in EDA playground and you still get this error.  

No *.vcd file found. EPWave will not open. Did you use '$dumpfile("dump.vcd"); $dumpvars;'?

You didn't answer the original poster's question.  I have the same problem.

[EDA Playground]

> For VHDL, you don't need to worry - it is all handled automatically.

When no waves appear, it is often because the simulation has timed out. (The maximum run time on EDA Playground is one minute). If this has happened, you'll see an error message to that effect in the log window.

If that doesn't solve it, then please post the URL of your playground and I'll have a look at it. One of the great things about EDA Playground is that you can easily share code by sharing the URL of your playground, which is unique.

Matthew