Compile error

[Prawin]

Hi team,

     I'm getting compile error when am compile multiple files.

   

   https://www.edaplayground.com/x/2p74

Regards,

prawin

[EDA Playground]

Hi Prawin,

I notice two things:

i) the tab containing ahb_test_pkg has no file extension (it's just called "ahb_test_pkg")

ii) there is no `include "ahb_test_pkg" anywhere (there needs to be)

Matthew
 

[Prawin]

Hi Matthew,

  I think package does't need include in top right , it just import in top 

[EDA Playground]

But before you can import a package you need to compile it (which you probably know). EDA Playground only compiles testbench.sv and design.sv. Anything else you want compiling needs to be `included into either of those two files.

Matthew

[Prawin]

ok thank you

[Prawin]

I'm getting this error on my uvm code ,

   System verilog keyword 'class' is not expected to be used in this context

can you please check once,

https://www.edaplayground.com/x/2p74,

Thanks,

prawin

[EDA Playground]

The trouble with `include is that `include file.sv is like opening file.sv in a texteditor, selecting all, copying, and pasting the contents of file.sv over the `include file.sv statement.

The error is not in m_agent_config.svh , but in the file included just before: look at the last line of s_seq_item.svh and you'll see the error staring you in the face.

Matthew

[Prawin]

I'll check once