Cannot instantiate abstract class error

[Stephen Lam]

Hi,

I'm working on a UVM example here: https://www.edaplayground.com/x/24Yk

I've defined a base testing virtual class (base_tester.sv). In my env.sv file I instantiate the base_tester object, then in my test (random_test.sv) I do a set_type_override to cast all factory creations of base_tester into the child class random_tester.sv

class random_test extends uvm_test;
  `uvm_component_utils(random_test);
 
  env env_h;
 
  function new (string name, uvm_component parent);
    super.new(name, parent);
  endfunction : new
 
  function void build_phase (uvm_phase phase);
    base_tester::type_id::set_type_override(random_tester::get_type());
    env_h = env::type_id::create("env_h", this);
  endfunction : build_phase
 
endclass : random_test

class env extends uvm_env;
  `uvm_component_utils(env);
 
  base_tester tester_h;
  coverage coverage_h;
  scoreboard scoreboard_h;

  function new (string name, uvm_component parent);
    super.new(name, parent);   
  endfunction : new

  function void build_phase(uvm_phase phase);
    tester_h  = base_tester::type_id::create("tester_h", this);
    coverage_h  = coverage::type_id::create("coverage_h", this);
    scoreboard_h = scoreboard::type_id::create("scoreboard_h", this);
  endfunction : build_phase
 
endclass : env

I'm am receiving this error from the compiler:

ERROR VCP2937 "Cannot instantiate abstract class: base_tester." "../../../../../home/runner/uvm-1.2/src/base/uvm_registry.svh" 66 28

My understanding is that since I declard set_type_override in random_test.sv to convert all base_testers to random_testers, I should not be hitting an error where the compiler thinks I am trying to instantiate the virtual base class. However the error seems to disagree. Can anybody see what I may be doing wrong?

[EDA Playground]

Yes. You cannot instantiate a virtual class. That's almost the definition of a virtual class.

[Stephen Lam]

I agree to that statement. What I cannot see, is where an I doing it? I have done a set_type_override to convert any base class factory calls to a child class. So why am I still seeing this error?

[EDA Playground]

The problem is here:

    `uvm_component_utils(base_tester)

It would seem that you cannot register a virtual component.

[Stephen Lam]

Huh. Somehow I feel like you should be able to register a virtual class component. So far my google fu hasn't revealed an answer.

So I am basically following a book example on how to create a reusable UVM env, in which you have a component that can be many variations of a virtual base component.

In the example, base_tester is the virtual class, and there are child classes random_tester and add_tester.

the UVM env needs to be reusable for tests that utilize both child classes. Therefore it instantiates the virtual base class using type_id::create(). The idea is to override that with set_type_override() in the test itself, which will turn all base_tester instances into the relevant child class. Therefore you don't actually instantiate the virtual class and you are safe.

However for the test itself to be able to call set_type_override(), it needs to know what base_tester is. And the only way it can know that in UVM methodology is if base_tester is registered to the factory using 'uvm_component_utils(base_tester).

If you cannot register a virtual component to the factory then this whole example breaks down. :(

Let me know what you think...I will possibly also repeat this issue to Verification Academy forum and see if anybody there knows.

[Stephen Lam]

The mystery is solved...turns out it is possible to register a virtual class, but only if you create a hacked version of the 'uvm_component_utils() macro. However this is not strictly UVM compliant.

In the example I'm working on, they must be doing some special modifications to enable abstract class registration, which doesn't work once applied onto the EDA Playground environment.

[EDA Playground]

Thank you -- that is interesting background info.

Matthew

[Stephen Lam]

Another interesting bit of information I acquired, and this comes directly from the author of the book I followed, whom I contacted yesterday:

It turns out that Mentor Graphics UVM libs support abstract class registration, something that does not align to the LRM. Users of their libs will not see this issue.

[EDA Playground]

Also interesting - thank you.

Matthew

[EDA Playground]

I spoke to John Aynsley - CTO of Doulos - and he said that the registration of abstract objects was introduced in UVM 1.2.

[Stephen Lam]

Interesting. Does that mean it is now part of the overall standard, and it's just that most tools don't support it yet?