SHA256 on FPGA

[Nurci Iani]

Hello guys,

i ve been trying to implement this sha256 alghorithm on my ARTY a7 35t, but for some reason it doesnt work.I will attach here my code and some pictures with the timing analysis on Vivado.

I noticed that i didint constrain my input and output delay and this is the only warning i receive. When i program my board with only the UART Module it works just fine without constraining the input and output delay. My question are as follows:

1.Do i need the input and output delay? Can you give me some videos or explanations on this subject

2.No paths are failing, but some of them have a bit of logic levels between them and some Fanout. should i be concerned about that. if yes how do i reduce them? Pipelining might be an idea.

3.Do i need to rewrite my code? If so, do you have any suggestions on how to change it. I am quite stuck right now. Thank you in advance!

https://www.edaplayground.com/x/gW_4