Getting access to dump.vcd file in VHDL

[momo doumbia]

Hello EDA Playground,

I have the following situation, namely I have a design in VHDL and I need the generated dump.vcd-file from the simulated design after downloading it. I have tried out that with

a Verilog-design, that works - I get a generated dump.vcd-file after the downloaded simulation, but for VHDL there isn't one.

 In Verilog there is also a function-call which generates the dump.vcd-file which isn't contained in VHDL.

Is there any possibility to get access to the dump.vcd-file in a VHDL-design or a ceriain

command to type in a script.

[EDA Playground]

This is a tool-use issue rather than an EDA Playground issue. It may be that one or more of the simulators on EDA Playground can output a VCD file for a VHDL simulation, but VCD is a Verilog thing, not a VHDL thing. 

One thing you could do is run a VHDL design with an SV testbench. Here is an example of how to do that: https://www.edaplayground.com/x/HESX .