VHDL based DUT and UVM

[Muhammad Hamza]

Hi;

I want to verify my design which is based on VHDL, and my DUT has one Inout port.

In which one signal is always treated input and two signals are output. 

I have created a VHDL wrapper in which I am assigning 1-to-1 connections. output signals are receiving fine from DUT. but the input signal is set to "U" constantly.

Anyone had experience with such a problem.

 or someone shares an example of UVM with VHDL-based DUT.

The key problem is Inout port.

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