VHDL design and testbench got no errors but not showing EPWave or Simulation

[Ghgeeerr Swaweeerr]

A VHDL design code for a remote-controlled garage door opener with sensors is provided to us. It has 8 states, 4 for each door. Testbench is not provided, and I did one (with help of testbench generator as well). The output should look something like this:

 

Below is the link of containing my codes and simulation:

https://www.edaplayground.com/x/J5S2

Kinda new to this. Don't know why it doesn't run.

Is there supposed to be a proper sequence of inputs for this specific code or am I missing some other inputs, such as those in testbench stimuli?

Hope someone could help analyzing the design and what I should put in the testbench stimuli cause I think I'm missing something. I tried different testbench but don't know where the mistake is. 

Thank you!

[EDA Playground]

Well, it doesn't compile at the moment. 

- I'd get rid of the configuration. That is adding nothing. 

- Are you part way through editing it? Get rid of the asterisks at the end of lines 57 and 60.

Now it compiles. However, to get it to run, you need to do something about the loop at line 39 that generates the clock. This will constantly keep generating "events" (changes scheduled for the future) and so your simulation ever stops (until, on EDA Playground, it times out).  You could put a fixed time in the "Run Time" box.  Or, a better solution would be to using a while loop in your clock-generator:

    clk_process :process
       begin

          while not STOP_CLOCK loop
            clk <= '0';
            wait for clk_period/4;   -- shouldn't this be  clk_period/2 ?
            clk <= '1';
            wait for clk_period/4;

          end loop;

          wait;
    end process;

and control the  STOP_CLOCK  signal from the "stimuli" process.

Matthew