Kernel-delta count overflow error

[HIMANSHU SHARMA]

https://edaplayground.com/x/MSpE

Hi while executing the above code I m getting Kernel-delta count overflow error , 

chosen simulator : Aldec Rivera,

since others needs validated account , so I cannot change my simulator .

please help in it.

Regards,

Himanshu

[EDA Playground]

A delta cycle is a VHDL term, but Riviera Pro seems to be using it for SystemVerilog, too. It's a simulation iteration. (At each simulation time, your simulator will have to iterate to ripple though all of the values until a steady state is reached. Then it advances to the next simulation time.)

You have a combinational loop: gnt_o depends on mask_next, but mask_next depends on gnt_o.