4 bit Carry Look Ahead Segmentation Fault

[Drew Kircher]

I wrote up a 4 bit Carry Look Ahead and fixed all of the errors I have recieved before but I can't find anything about this segmentation fault I keep getting

"ALIB: Library "work" attached.

work = /home/runner/work/work.lib
./run.sh: line 7: 16 Segmentation fault (core dumped) vcom '-2008' design.vhd testbench.vhd
Exit code expected: 0, received: 139"

https://www.edaplayground.com/x/uxjs

[EDA Playground]

This is a bug In the simulator, not in EDA Playground. 

In my experience, such things are caused usually by errors in the HDL code. (The simulator should report that error, not crash, so it is a bug in the simulator too.) So, the thing to do in this case is to try a different simulator. GHDL reports an error at line 33 of your testbench (a missing '-'); Questa reports an error at line 18 of your design (too many 'd's).

[Drew Kircher]

I went with what you suggested and fixed these two errors you found using the other simulators, GHDL now tells me "cannot find entity or configuration testbench". I was unable to use Questa but I fixed the error it reported as you kindly showed me. I fixed a couple other typos with my code and I can get it to compile now bit I have run into this: 

DAGGEN WARNING DAGGEN_0523: "The source is compiled without the -dbg switch. Line breakpoints and assertion debug will not be available."

ELAB1 WARNING ELAB1_0026: "There is no default binding for component "Full_Adder_Part". (No entity named "Full_Adder_Part" was found)." "design.vhd" 37 0

dmesg: read kernel buffer failed: Operation not permitted
dmesg: read kernel buffer failed: Operation not permitted
# Aldec, Inc. Riviera-PRO version 2020.04.130.7729 built for Linux64 on June 10, 2020.
# HDL, SystemC, and Assertions simulator, debugger, and design environment.
# (c) 1999-2020 Aldec, Inc. All rights reserved.
# VSIM: Error: Unknown library unit 'testbench' specified.
# VSIM: Error: Simulation initialization failed.

[EDA Playground]

Your testbench is called "testbench_Carry_Look_Ahead" - ie that's the top-level entity name, so that's what needs to go in the "Top entity" box. (Unlike Verilog, VHDL can't wok that out for itself.) 

There is no code for Full_Adder_Part, which is why you are getting your error above. Think of an entity/architecture as the chip and the component as the socket. There is a VHDL construct called a "configuration" which allows you to specify which entity/architecture gets "bound" to which component (ie which chip goes in which socket). If you don't have such a thing, VHDL can bind entities/architectures to components using the "default binding" rules. These are:

1) the name of the entity and component must be the same

2) the names and types of all the ports must be the same

3) whatever architecture is compile last is used. (Usually, there is only one architecture anyway.) 

There is no code for Full_Adder_Part, so none of the above rules can be applied and so you get your error. You need to supply the code for Full_Adder_Part.

I don't know who is teaching you VHDL, but using components became optional in 1993 (ie nearly 30 years ago). They are not used very often - they are only used now in some specific circumstances. Instead, you can do so-called "direct instantiation", like this: 

    https://www.edaplayground.com/x/MjA2

(This still won't compile, because you're still missing the code for Full_Adder_Part.