Design unit "moduleName" instantiated in work.*testbench Name* not found in searched libraries: work.

[Ahmad salman]

I am writing a systemVerilog simulation for a single-cycle processor for MIPS:

this is the module code:

module new_top(input   logic clk, reset,            

     output  logic       memwrite,

         output logic alusrca, alusrcb, regwrite, jump, branch,

               output logic [1:0]  memtoreg, aluop, regdst,

         output logic [31:0] pc, instr, readdata, writedata, dataadr,

         output logic pcsrc, zero

     );

logic [2:0]  alucontrol;

    mips mips (clk, reset, pc, instr, memwrite, dataadr, writedata, 

    readdata, pcsrc, zero, alusrca, alusrcb, regwrite, jump, branch, memtoreg, aluop, regdst, alucontrol);

      

    imem imem (pc[7:2], instr);  

    dmem dmem (clk, memwrite, dataadr, writedata, readdata);

    

endmodule

This is the code for the Testbench:

module mips_lite_testbench();

initial

  begin

$dumpfile("dump.vcd");

$dumpvars(1);

  end

  logic clk, reset;            

  logic memwrite;

  logic alusrca, alusrcb, regwrite, jump, branch;

  logic [1:0]  memtoreg, aluop, regdst;

  logic [31:0] pc, instr, readdata, writedata, dataadr;

  logic pcsrc, zero;

  

  new_top dut ( clk, reset, memwrite, alusrca, alusrcb, regwrite, jump, branch, memtoreg, aluop, regdst, pc, instr, readdata, writedata, dataadr, pcsrc, zero );

  

    initial begin

  for( int i = 0; i < 100; i++ )

begin

#10; clk = ~clk;

end

end

  

endmodule

This is the error message:

VSIMSA: Configuration file changed: `/home/runner/library.cfg'
ALIB: Library "work" attached.
work = /home/runner/work/work.lib
MESSAGE "Pass 1. Scanning modules hierarchy."
WARNING VCP2515 "Undefined module: new_top was used. Port connection rules will not be checked at such instantiations." "testbench.sv" 15 161
MESSAGE "Pass 2. Processing instantiations."
MESSAGE "Pass 3. Processing behavioral statements."
MESSAGE "Running Optimizer."
MESSAGE "ELB/DAG code generating."
MESSAGE "Unit top modules: mips_lite_testbench."
MESSAGE "$root top modules: mips_lite_testbench."
SUCCESS "Compile success 0 Errors 1 Warnings Analysis time: 0[s]."
ALOG: Warning: The source is compiled without the -dbg switch. Line breakpoints and assertion debug will not be available.
done
# Aldec, Inc. Riviera-PRO version 2020.04.130.7729 built for Linux64 on June 10, 2020.
# HDL, SystemC, and Assertions simulator, debugger, and design environment.
# (c) 1999-2020 Aldec, Inc. All rights reserved.
# ELBREAD: Elaboration process.
# ELBREAD: Error: ELBREAD_0081 testbench.sv (15): Design unit new_top instantiated in work.mips_lite_testbench not found in searched libraries: work.
# ELBREAD: Error: Elaboration process completed with errors.
# VSIM: Error: Simulation initialization failed.
Finding VCD file...
No *.vcd file found. EPWave will not open. Did you use '$dumpfile("dump.vcd"); $dumpvars;'?
Done

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