SV/UVM Aldec License Error

[Hitesh Barod]

Hi,

I'm seeing SV/UVM run time errors with Aldec as follows

# Aldec, Inc. Riviera-PRO version 2025.04.139.9738 built for Linux64 on May 30, 2025.
# HDL, SystemC, and Assertions simulator, debugger, and design environment.
# (c) 1999-2025 Aldec, Inc. All rights reserved.
# ELBREAD: Elaboration process.
# ELBREAD: Error: You do not have a valid license to simulate module "uvm_1_2.\uvm_pkg uvm_bottomup_phase \" using SystemVerilog advanced verification features. Contact Aldec for ordering information - sa...@aldec.com.
# ELBREAD: Error: Elaboration process completed with errors.
# VSIM: Error: Simulation initialization failed.
Exit code expected: 0, received: 1

[Hitesh Barod]

looks like an expired license issue for Aldec, kindly see.

[EDA Playground]

Unfortunately, we have had to restrict access to Riviera Pro due to unauthorised use. We are not sure what the final outcome will be at this stage.