32-bit ALU VHDL code

[Xenia Sotiriadou]

Hi,

I am trying to create a 32-bit ALU for an assignment, but I am getting these error messages that I don't quite understand: 

COMP96 ERROR COMP96_0143: "Object "Result" cannot be written." "design.vhd" 15 2

COMP96 ERROR COMP96_0724: "',' or ')' expected." "testbench.vhd" 12 28
COMP96 ERROR COMP96_0015: "';' expected." "testbench.vhd" 12 31
COMP96 ERROR COMP96_0019: "Keyword 'when' expected." "testbench.vhd" 12 65
COMP96 ERROR COMP96_0015: "';' expected." "testbench.vhd" 12 65
COMP96 ERROR COMP96_0019: "Keyword 'end' expected." "testbench.vhd" 12 65
COMP96 ERROR COMP96_0016: "Design unit declaration expected." "testbench.vhd" 12 66
COMP96 ERROR COMP96_0019: "Keyword 'of' expected." "testbench.vhd" 16 22
COMP96 ERROR COMP96_0018: "Identifier expected." "testbench.vhd" 16 22

Here is my code and testbench:

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_signed.ALL;

entity alu is

port(

    A, B: in std_logic_vector(31 downto 0);

    opcode: in std_logic_vector(2 downto 0);

            Result: in std_logic_vector(31 downto 0) 

            );

end entity alu;

architecture dataoperations of alu is

begin 

Result <= A + B when opcode="1010" 

    else A - B when opcode="1000"

    else abs(A) when opcode="1011"

    else -A when opcode="1101"

    else abs(B) when opcode="0001"

    else -B when opcode="1001"

    else A or B when opcode="0110"

    else not A when opcode="1111"

    else not B when opcode="0101"

    else A and B when opcode="1100"

    else A xor B when opcode="0010";

end architecture dataoperations;

 

testbench:

library IEEE;

use IEEE.std_logic_1164.all;

entity mytestbench is

end entity mytestbench;

architecture test of mytestbench is

signal in1, in2, out1: std_logic_vector (31 downto 0);

    signal in3: std_logic_vector (2 downto 0);

begin

g1: entity work.alu(dataoperations)

    port map (A <= in1, B <= in2; opcode <= in3, Result <= out1);

    in1 <= "0001", "0FAF" after 20 ns, "F000" after 40 ns;

    in2 <= "0100", "7FFF" after 10 ns, "FFFF" after 30 ns;

    in3 <= "00";

end architecture test;

 

Can someone please help?

[Stefano Devecchi]

"One of the great things about EDA Playground is that it allows you to share code by sharing the URL of that code (which is unique). Nobody can help you if they cannot see the code. (The error is a mistake in your code.)"

cit. 

[Xenia Sotiriadou]

https://www.edaplayground.com/x/piU6

Here is the full code

[glenn.c...@gmail.com]

Hi,

You have quite a few errors in your code (in both the design unit and testbench).

If you are new to VHDL I would recommend going through the error messages one-by-one to understand what is causing them.

To help with the first one:

COMP96 ERROR COMP96_0143: "Object "Result" cannot be written." "design.vhd" 15 2

This is saying that the port 'Result' at line 15 character 2 can not be written to. This is because it has been declared as in input in the entity declaration. You probably meant for this to be an output.

If you work through the other error messages one by one you will eventually get there, though I am not sure your stimulus assignments to port A and B will work as you are expecting.

Glenn.

[L186_Ritesh Kumar Sharma]

The main problems r that u have declared Result as input , and later in the vhdl code mentioned the result as output, so in the port part u have to declare the Result as output like this 

Result : out std_logic_vector(31 downto 0) 

and mention the type of architecture u r using in the VHDL code