synopsys license error

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Jagat Shah

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Jul 31, 2016, 8:50:20 PM7/31/16
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HI ,

    I am unable to run my test on synosys tool anymore, getting this license error, I tried running same code on cadence and getting weird compile errors.
I was able to run this code on synopsys reliably for a while, can you help please?

Jagat



[2016-07-31 20:44:01 EDT] vcs -licqueue '-timescale=1ns/1ns' '+vcs+flush+all' '+warn=all' '-sverilog' +incdir+$UVM_HOME/src $UVM_HOME/src/uvm.sv $UVM_HOME/src/dpi/uvm_dpi.cc -CFLAGS -DVCS design.sv testbench.sv && ./simv +vcs+lic+wait
Chronologic VCS (TM)
Version J-2014.12-SP1-1 -- Mon Aug 1 00:44:02 2016
Copyright (c) 1991-2014 by Synopsys Inc.
ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

Fatal License Error.
Inconsistent Encryption code in license file.
Make sure that your LM_LICENSE_FILE points to the correct server
Please contact VCS Customer Support at 1-800-VERILOG for more information.

CPU time: .102 seconds to compile
Exit code expected: 0, received: 255
Done

EDA Playground

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Aug 1, 2016, 3:58:22 AM8/1/16
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Hi Jagat,

Sorry for your inconvenience. We switched over from one licence to another this morning (31/7 to 1/8). That may have been the cause. I have just tried it out now and it worked fine. Let me know if you're still having problems.

Matthew

Jagat Shah

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Aug 1, 2016, 10:30:29 AM8/1/16
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Thanks Matthew, it works now.

Jagat

Luke Lovegrove

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Aug 31, 2016, 9:02:27 PM8/31/16
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Hi there,

I know this is an older post now, but I am having the same issue!

Any help much appreciated!

Chronologic VCS (TM)
Version J-2014.12-SP1-1 -- Thu Sep 1 00:56:40 2016

Copyright (c) 1991-2014 by Synopsys Inc.
ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

Fatal License Error.
Inconsistent Encryption code in license file.
Make sure that your LM_LICENSE_FILE points to the correct server
Please contact VCS Customer Support at 1-800-VERILOG for more information.

CPU time: .202 seconds to compile
Exit code expected: 0, received: 1
Done

EDA Playground

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Sep 2, 2016, 1:30:12 PM9/2/16
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We switched to a new Synopsys licence on 1st of September. I did test it yesterday and it seemed to be working fine. I have just tried it again and ditto. Are you still having the problem?

Matthew

rakesh babu

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Aug 1, 2019, 5:25:39 AM8/1/19
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Hi,

I am facing the same issue. Any help on this?

Thanks,
Rakesh

                         Chronologic VCS (TM)
         Version J-2014.12-SP1-1 -- Thu Aug  1 09:20:48 2019

               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.

CPU time: .072 seconds to compile

Exit code expected: 0, received: 1
Done

G.Somesh Gurumoorthy

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Aug 1, 2019, 8:36:49 AM8/1/19
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Hi,

I am still facing the issue . Can you please have a look into this ?

Error Message : 

[2019-08-01 08:36:47 EDT] vcs -licqueue '-timescale=1ns/1ns' '+vcs+flush+all' '+warn=all' '-sverilog' '+UVM_VERBOSITY=UVM_HIGH' +incdir+$UVM_HOME/src $UVM_HOME/src/uvm.sv $UVM_HOME/src/dpi/uvm_dpi.cc -CFLAGS -DVCS design.sv testbench.sv && ./simv +vcs+lic+wait '+UVM_VERBOSITY=UVM_LOW' '+through_uvm_reg'

Warning-[LNX_OS_VERUN] Unsupported Linux version
Linux version 'CentOS Linux release 7.1.1503 (Core) ' is not supported on
'x86_64' officially, assuming linux compatibility by default. Set
VCS_ARCH_OVERRIDE to linux or suse32 to override.
Please refer to release notes for information on supported platforms.


Warning-[LINX_KRNL] Unsupported Linux kernel
Linux kernel '3.13.0-71-generic' is not supported.
Supported versions are 2.4* or 2.6*.

Chronologic VCS (TM)
Version J-2014.12-SP1-1 -- Thu Aug 1 12:36:48 2019

Copyright (c) 1991-2014 by Synopsys Inc.
ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[UNK_COMP_ARG] Unknown compile time plus argument used
Unknown compile time plus argument 'UVM_VERBOSITY=UVM_HIGH' is ignored.

+ use `+plusarg_save' to bind in runtime plusargs;
+ use `+plusarg_ignore' to suppress this message.

Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.

CPU time: .063 seconds to compile

Exit code expected: 0, received: 1

On Friday, September 2, 2016 at 11:00:12 PM UTC+5:30, EDA Playground wrote:

Marcus Bosco

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Aug 2, 2019, 1:04:34 AM8/2/19
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Hi

I simulated it today facing the same issue!

[2019-08-02 00:58:12 EDT] vcs -licqueue '-timescale=1ns/1ns' '+vcs+flush+all' '+warn=all' '-sverilog' +incdir+$UVM_HOME/src $UVM_HOME/src/uvm.sv $UVM_HOME/src/dpi/uvm_dpi.cc -CFLAGS -DVCS design.sv testbench.sv && ./simv +vcs+lic+wait

Warning-[LNX_OS_VERUN] Unsupported Linux version
Linux version 'CentOS Linux release 7.1.1503 (Core) ' is not supported on
'x86_64' officially, assuming linux compatibility by default. Set
VCS_ARCH_OVERRIDE to linux or suse32 to override.
Please refer to release notes for information on supported platforms.


Warning-[LINX_KRNL] Unsupported Linux kernel
Linux kernel '3.13.0-71-generic' is not supported.
Supported versions are 2.4* or 2.6*.

Chronologic VCS (TM)
Version J-2014.12-SP1-1 -- Fri Aug 2 04:58:13 2019

Copyright (c) 1991-2014 by Synopsys Inc.
ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.

CPU time: .059 seconds to compile

Exit code expected: 0, received: 1
Done

Please CHeck on the same!

On Friday, September 2, 2016 at 11:00:12 PM UTC+5:30, EDA Playground wrote:
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