Problem with simulating a VCO

[Bernard Mentink]

Hi All,

Very new to Verilog, but am having a go at simulating a PLL, and part of that is simulating the VCO.

When I add the following line:

always #(1500 - Vctl) vco <= ~vco;

.. in the testbench code, it complains about not having a $timescale set. (Vctl is the output from a module, which nneds to control the VCO frequency/period)

If I add the line:

`timescale 1na/10ps

.. at the top of the testbench code, it then complains that my modules may have differing timing ...

I tries putting the same line in my module file, but then back to original error: How  do I resolve this?

Thanks

[EDA Playground]

Hi Bernard,

You of the great things about EDA Playground is that it is easy to share code by simply emailing (or tweeting or messaging or whatever) the URL. It might be easier to help you were you to do that for your example.

However, there are some simple rules re `timescale:

i) if any file has a `timescale, then the first file compiled must have one

ii) a `timescale directive applies across file boundaries (ie until the next one is encountered)

iii) if more than one `timescale directive is encountered then the smallest value of the precision is used for all the files

So, for example, if we have the following files:

   file_a.v contains `timescale 1ns/1ns
   file_b.v contains `timescale 10ns/1ps
   file_c.v contains no `timescale directive

then if we compile in this order:

   file_a.v file_b.v file_c.v

the precision will be 1ps and #1 will represent 1ns in file_a.v and 10ns in file_b.v and file_c.v. If we compile in this order:

   file_b.v file_a.v file_c.v

the precision will be again be 1ps and #1 will represent 1ns in file_a.v and file_c.v and 10ns in file_b.v. If we try to compile in this order:

   file_c.v file_a.v file_b.v

we'll find that file_a.v will terminate compilation with an error because file_c.v has no `timescale while file_a.v does.

In EDA Playground you cannot control the compilation order, so I would recommend putting a `timescale directive at the top of all your files or none (if you're not fussed about specific timing).

I hope that helps.

Matthew

[Bernard Mentink]

Thanks, that explanation helps. However my issue remains:

I get the following error:

[2016-10-10 15:14:11 EDT] Opening EPWave...
Error launching EPWave: [Could not parse file: $timescale not found in the header.]. Could not load './dump.vcd'
Done

The code is here:

module test; reg vco, ref, rstN; wire up, down; wire [15:0] Vctl; //-- Instantiate the Phase comparator pfd phaseC( .up(up), .dn(down), .vco(vco), .ref(ref), .rstN(rstN) ); // Instantiate Loop Filter loopFilter loopF( .sampleClk(vco), .up(up), .dn(down), .Vctl(Vctl) ); // Get a clock going continuous always #1000 ref <= ~ref; always #(1500 - Vctl) vco <= ~vco; initial begin $dumpfile("dump.vcd"); $dumpvars(1,test); vco = 1'b0; ref = 1'b0; rstN = 1'b0; // Release reset #10 rstN = 1'b1; #30120; $finish; end endmodule

[Bernard Mentink]

Found my issue.

I just had to ensure that the loopF module initialised Vctl to "0" as it was "X" before the 1st VCO clock  ... that upset the simulation ...

Thanks for the help ..

Bernie

PS: There does not seem to be a way to edit old posts in this forum ..

[EDA Playground]

What are you wanting to do? Delete your code?

[Bernard Mentink]

Not sure what you mean? I just need to know how to edit posts once they are submitted .... all other forums allow you to do this, i.e to correct a mistake ..

I have another question though.

I would like to try and graph the VCO frequency versus time, is there a way to do that? ..... i.e want to view the PLL response/overshoot ....

[EDA Playground]

It doesn't look like you can edit posts.

There is nothing on EDA Playground for plotting. Your best bet is to output the values to a file and run the simulation with the "Download files after run" box checked. You can then load the file into some SW that plots graphs (Excel, Matlab, etc).

Matthew

[Bernard Mentink]

Ok, thanks.

I downloaded and looked at the dump.vcp file created, but I don't understand the format to decode it for Excel ...

Can you help with that at all?

Thanks,

Bernie

[Bernard Mentink]

also, it seems the simulation testbench doesn't handle negative numbers very well. If Vctl is a 16 bit negative number (FFF2), then the statement

always #(5400 - Vctl) vco <= ~vco;

doesn't do as expected .... (a subtraction of a negative number should result in Vctl being added to 5400), it doesn't ... it treats it as unsigned ..

The statement above only works for positive numbers ..

Cheers,

Bernie

[EDA Playground]

The VCD isn't human readable. I meant explicitly opening a file using $fopen and then writing to it using $fdisplay or $fwrite etc. This file will be accessible in the zip file download if you tick the "Download files after run" box.

[EDA Playground]

You need to declare Vctl as 'signed' ('wire signed [15:0] Vctl;'). If you mix signed and unsigned arithmetic in Verilog, unsigned arithmetic is performed.

[Bernard Mentink]

Thanks, but where do I find the documentation for all the $... commands? .. and how do I write the file at a regular time increment ..

[Bernard Mentink]

Thanks, that worked great ..... appreciate all the help ...

[EDA Playground]

Verilog has quite powerful file reading and writing capability. It is not really possible to teach you that in a forum post; to find out about $fopen etc, you need some kind of textbook or Google or some training (my company - Doulos - sells Verilog training). There are a couple of ways of writing to files at regular time intervals: (i) write each line inside a loop with a delay in it or (ii) use $fmonitor (via a textbook or Google or training).

[Bernard Mentink]

Thanks, I will google .. had a quick try ..

I notice that $fmonitor is not supported though .. will have to use $write

SORRY: testbench.sv:50: task $fmonitor() is not currently implemented.

[EDA Playground]

Which simulator are you using? I can't believe Riviera Pro doesn't support $fmonitor. Likewise Incisive or VCS (if you validate your account).

[Bernard Mentink]

I am using Icarus Verilog 0.9.7 ... guess it doesn't support it .. I havn't tried any of the commercial simulators as I am doing everything with the free tools ..

(My current FPGA builds uses Linux yosys etc and I have a cpu and several peripherals working together quite nicely ..)

By the way, when I use Yosys in EDA Playground I get the following error when trying to display the circuit .. (i.e "show Diagram" checkbox ticked)

-- Running pass `show -colors 1 -viewer touch' --
9. Generating Graphviz representation of design.
ERROR: For formats different than 'ps' only one module must be selected.
Finding SVG file...
No *.svg file found. Diagram will not open.
Done

[EDA Playground]

I added the ability to display a Yosys diagram quite recently, so it's nice to hear someone is using it. But, as I am a logic designer not a web programmer, there could easily be some bug. Can you post the URL of the code that is giving this error?