Getting power results from verilog code

[Shubham Gupta]

I made a LFSR circuit using the Verilog and I want to know the power consumption of that circuit, so can anyone tell me how can i achieve it 

[EDA Playground]

A couple of ways spring to mind: use a commercial power simulation tool (not available on EDA Playground, unfortunately). Look into the documentation of the FPGA/IC process you intend to use and you will surely find information about how to estimate power consumption.

[Shubham Gupta]

Can you suggest any free tool or simulation software where I can get my power consumption results?

[Vikramaditya Kundur]

Hello Shubham,

To calculate a power, you need to have a target technology and a synthesized netlist. Then you can get a saif files from your simulation to get the actual power numbers using the synthesized setlist. There is no free tool for this type of calculation.

You could model the power calculation using real number inside the verilog file. That is how you can get the power numbers from any free simulation. A very simple example (pseudo code).

module test ; 

real add_block = 0;  

dut add_block(a,b,sum,carry);

initial 

begin

$display ("add_block is %f", add_block);

...

end

endmodule

module add_block(a,b,sum,carry);

....

if(( a != 0) && (b !=0)

    add_block = 3.53;

if(( a == 0) && (b !=0)

    add_block = 1.78;

 if(( a != 0) && (b ==0)

    add_block = 1.43;   // discrete hand calculation 

$display ("add_block is %f", add_block);

endmodule

hope this helps.

Thanks,

-Vikram