What is *.vcd file and how can I fix it?

[Mr. Nobody]

When I click RUN button while "Open EPWave after run", I recieved below:

[2022-04-21 13:02:45 UTC] iverilog '-Wall' design.sv testbench.sv && unbuffer vvp a.out
Finding VCD file...
No *.vcd file found. EPWave will not open. Did you use '$dumpfile("dump.vcd"); $dumpvars;'?
Done

[glenn.c...@gmail.com]

if you care to share the link to the playground, volunteers will be able to have a look.

[Mr. Nobody]

Thanks! This is my link:

https://www.edaplayground.com/x/F7KM

[EDA Playground]

A VCD file ("Value Change Dump" file) is a file which contains all the values of the wires and regs in a simulation over time so that they can be displayed on a waveform display. 

You have ticked the "Open EPWave after run" box, so EDA Playground tries to over a waveform display. However, you have not included any code to output a VCD file. The missing code is reported by the error message: $dumpfile("dump.vcd"); $dumpvars;'. These two lines need to be in an initial block in your testbench. 

You don't have a testbench at the moment. I'm not sure whether that is because you haven't got round to writing it yet or whether you don't appreciate the need for one. The name of you design module suggests the latter. You do need a testbench: some code that at least drives the inputs of your design so that you can test it. Your design looks like a full adder, so your testbench wants to be driving all combinations of a, b and cin. (Look at some of the simpler Verilog/SystemVerilog examples on EDA Playground for examples of simple testbenches.)