Using `define text macro

[Tapajara]

I am still a newbie to Verilog and it seems that `define text macros can't be used in synthesizable code. When I try to assign a value via one of these, Icarus and other tools complain that it couldn't be bound. Using the following declaration and assignment:

  `define OpcMor 0

  output reg [2:0] StaR,  //Status Register
    StaR <= OpcMor;

I get the following error:

design.sv:52: error: Unable to bind wire/reg/memory `OpcMor' in `Opc'

[EDA Playground]

    StaR <= `OpcMor;

You need the backquote. This is different to C.