Interface signals can't see on waveform

[Vukasin Polic]

Hi,

I wanted to check something inside the basic testbench but found some issues.
I used and modified this testbench:
https://www.edaplayground.com/x/8Nyg

For the simulator, I used Aldec Riviera Pro.

Inside the interface, besides other signals, I have two signals that I want to check:
  wire data;
  logic data_lq[slave_num];

Both of these signals are inout signals.
When I run a simulation and open waveform, inside Get Signals to Display, in .inf, I can't see these signals (first screenshot).

Is this an issue with the simulator, EDA, or something else with the code?

Does anyone know what could be the cause?

I appreciate any help you can provide.
Vukasin

[Vukasin Polic]

I tested this case in other simulators, and I found this:
- For the Cadence Xcelium works, I see both signals on a wave;
- For the Simens Questa, only works for wire signal, but not for logic data_lq[slave_num] signal (and I need to remove modports);
- For the Synopsys VCX, it is the same case as the Simens Questa.