Yosys diagrams with multi-module hierarchial verilog file

[Roberto Muscedere]

Hello. I'm teaching a class in digital logic design with some brief intro to verilog and so far this site is working great. I personally use synopsys for my synthesis, but since I can't offer this to my students, this site offers an easy way to synthesis verilog into a readable schematic. I have come upon an issue though, I just tried to add in a multi-module hierarchical verilog file and it gives me an error just before showing the diagram when using Yosys 0.3 w/ ABC cell library:

...
14. Generating Graphviz representation of design.
ERROR: For formats different than 'ps' only one module must be selected.
Finding SVG file...
No *.svg file found. Diagram will not open.
Done

I figure this has to do with the fact that the site doesn't know which module to show me.

Here is the verilog code, just a 4 bit ripple carry adder:

module HA(output S, C, input x, y);
xor (S, x, y);
and (C, x, y);
endmodule
module FA (output S, C, input x, y, z);
wire S1, C1, C2;
HA HA1 (S1, C1, x, y);
HA HA2 (S, C2, S1, z);
or G1 (C, C2, C1);
endmodule
module RC4A(output [3: 0] Sum, output C4, input [3: 0] A, B, input C0);
wire C1, C2, C3;
FA
  FA0 (Sum[0], C1, A[0], B[0], C0),
  FA1 (Sum[1], C2, A[1], B[1], C1),
  FA2 (Sum[2], C3, A[2], B[2], C2),
  FA3 (Sum[3], C4, A[3], B[3], C3);
endmodule

I think this can be avoided if an option was given to flatten the design to one module on the last stage of synthesis.

Thanks.

[EDA Playground]

Hi Roberto,

I noticed this myself last month, but didn't realise that the fix might be this straight-forward. Thank you for the info. I will add it to the list of things to do.

I'm glad to hear you're finding EDA Playground useful.

Matthew