Adding command-line arguments to vvp

[James Smith]

Hi,

I'm trying to modify a lab activity that we normally run from the command line with iVerilog and it requires using command-line arguments with the + switch:

vvp a.out +a=1 +b=0 +c=0

we're using the $value$plusargs system task to pass in the command line arguments to vvp.  But when I run the Verilog script in EDA playground with the Run Options set to +a=1,+b=0,+c=0 I get an error:

[2020-11-11 05:34:06 EST] iverilog '-Wall' design.sv testbench.sv && unbuffer vvp '+a=1,+b=0,+c=0' a.out
+a=1,+b=0,+c=0: Unable to open input file.
Exit code expected: 0, received: 1

I'm trying to pass those arguments like this 

      flag = $value$plusargs("a=%b", a);

Am looking for suggestions on a recommended way to pull this off properly on EDA Playground.

thanks!

James

Here's the complete Verilog file:

// Code your testbench here

// or browse Examples

//`timescale 1 ns/10 ps // time units

module LabI_part7;

  

reg a, b, c, flag ;  // reg without size means 1-bit

wire z, notOutput, Aout1, Aout2, lowerInput, OrIn1, OrIn2;

  integer i, j, expect; //  testing

  

 

// Describe the gates in the circuit

  not my_not(notOutput, b);

  and my_and(Aout1, a, lowerInput);

  and my_and2(Aout2, c, b);

  or my_or(z, OrIn1, OrIn2);

  

  assign lowerInput = notOutput;

  assign OrIn1 = Aout1;

  assign OrIn2 = Aout2;

 

initial

begin

      

      flag = $value$plusargs("a=%b", a);

      flag = $value$plusargs("b=%b", b);

      flag = $value$plusargs("c=%b", c);

  a =1; b=0; c=0; // set the signals to single values

      #20 $display("a=%b b=%b z=%b", a, b, z);

       $finish;

end

endmodule

[James Smith]

Whoops... wrong file

// Code your testbench here

// or browse Examples

//`timescale 1 ns/10 ps // time units

module LabI_part7;

  

reg a, b, c, flag ;  // reg without size means 1-bit

wire z, notOutput, Aout1, Aout2, lowerInput, OrIn1, OrIn2;

  integer i, j, expect; //  testing

  

 

// Describe the gates in the circuit

  not my_not(notOutput, b);

  and my_and(Aout1, a, lowerInput);

  and my_and2(Aout2, c, b);

  or my_or(z, OrIn1, OrIn2);

  

  assign lowerInput = notOutput;

  assign OrIn1 = Aout1;

  assign OrIn2 = Aout2;

 

initial

begin

      

      //flag = $value$plusargs("a=%b", a);

      //flag = $value$plusargs("b=%b", b);

      //flag = $value$plusargs("c=%b", c);

  //a =1; b=0; c=0; // set the signals to single values

      #20 $display("a=%b b=%b c=%c z=%b", a, b, c, z);

       $finish;

end

endmodule

[EDA Playground]

Please could you post the URL of this code?

[EDA Playground]

Eda Playground <getedapl...@gmail.com>

4:48 PM (0 minutes ago)

to James

Hi James,

This seems to work: make the "Run Options"

    a.out +a=1 +b=0 +c=0