Unable to bind wire/reg/memory 'test' in 'cordic_test'

[Nikola Radakovic]

I am trying to start Wave simulator , but when I click run , my Log window

generates the error below: 

2017-06-14 10:24:49 EDT] iverilog '-Wall' design.sv testbench.sv && unbuffer vvp a.out
testbench.sv:28: error: Unable to bind wire/reg/memory `test' in `cordic_test'
1 error(s) during elaboration.
Exit code expected: 0, received: 1
Done

[EDA Playground]

Hi Nikola,

Each "Playground" on EDA Playground has a unique URL. One of the great things about EDA Playground is that it is possible to share code by sharing that URL. I pasted your code into a new playground and could not reproduce your error. Please could you share the URL of your playground? (And that would have been a lot easier than cutting and pasting your code into files and attaching them to a post.)

Matthew