Page reload problem

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EDA Playground

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Jun 30, 2021, 6:35:34 AMJun 30
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Some error resulting in page reloads for some users when they click on run. I am looking into it. Sorry for the inconvenience.

If this is happening to you, restricting yourself to the Aldec Riviera Pro and the open source EDA tools seems to be a workaround.

taufeeq khan

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Jul 12, 2021, 6:27:47 AMJul 12
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 Cannot open `include file "/tools/questa-/2020.3/questasim/ovm-2.1.2/../verilog_src/ovm-2.1.2/src/uvm_pkg.sv".
** Error: top.sv(2): Cannot open `include file "/tools/questa-/2020.3/questasim/ovm-2.1.2/../verilog_src/ovm-2.1.2/src/uvm_macros.svh".
** Error: top.sv(5): Cannot open `include file "/tools/questa-/2020.3/questasim/ovm-2.1.2/../verilog_src/ovm-2.1.2/src/intf.sv".
** Error: top.sv(6): Cannot open `include file "/tools/questa-/2020.3/questasim/ovm-2.1.2/../verilog_src/ovm-2.1.2/src/adder.sv".
** Error: ** while parsing file included at top.sv(7)
** at seqitem.sv(3): (qverilog-2163) Macro `uvm_object_utils is undefined.
** Error: (qverilog-13069) ** while parsing file included at top.sv(7)
** at seqitem.sv(3): near "(": syntax error, unexpected '(', expecting function or task or "SystemVerilog keyword 'pure'".
End time: 15:51:57 on Jul 12,2021, Elapsed time: 0:00:01
Errors: 6, Warnings: 0
I got some  error  during simulation time  please tell me  why is it giving a error
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