Announcement of update to the virtual platform

[Adrian Herrera]

Hi all,

Arm is planning to provide an update to the virtual platform proposed in the Industrial Challenge 2022 [1] in the coming weeks.

This platform, as described in the challenge paper, is constructed from two open-source tools: gem5 and ATP Engine.

• Gem5: a computer architecture simulator that provides configurable models of processors, memory, and other hardware system components with a balanced trade-off between accuracy and simulation efficiency. It can run an observable simulation on top of them, capable of executing Linux and other complex software.
• ATP Engine: a traffic modeling tool that can be connected to gem5. It can model interfaces and outgoing traffic from processors and other system components, such that the modeled traffic adapts to the perceived capacity of the system.

This platform is mainly intended to facilitate exploring optimizations around shared resource interference monitoring and performance isolation. It does so by providing observable and controllable simulations, in which the challengers can configure different traffic scenarios and resource allocations and analyze the effect on the performance of individual traffic flows, CPU applications, as well as the system.

The gem5 repository of the challenge contains two virtual platform configurations [2] that challengers can use as a baseline for simulation. The motivation for this update stems from the following observations:

• Performance isolation mechanisms in system components are lacking in gem5, so it is costly to explore different configurations towards optimization, since challengers must implement their own mechanisms.
• While there is a readily usable virtual platform configuration integrating ATP Engine with gem5, the ATP traffic models for the processing tasks in the challenge are not provided, and crafting these ATP traffic models is not trivial.

This update provides the following value:

• Cache partitioning policies have been modeled in gem5. Specifically, challengers can now configure the caches with either standard way-partitioning or maximum-capacity partitioning, as defined in the Arm Memory Partitioning and Monitoring (MPAM) extension.
• A partition ID has been added to memory requests in gem5. This is used by resources, for now caches, to resolve which partition corresponds to the software process that issued the memory request.
• ATP Engine now hosts ATP traffic models for all the challenge processing tasks outside of the CPU, that is, excluding SLAM and Frame Preparation. This covers traffic models for all device and accelerator traffic. The ATP Engine can now also drive the partition ID supported in gem5, so the modeled traffic can be subject to partitioning.

With this update, Arm hopes to further facilitate the exploration of performance isolation and monitoring strategies for challengers. The update provides significant value by addressing the lack of performance isolation mechanisms in gem5 and the absence of ATP traffic models for the processing tasks in the challenge. By modeling cache partitioning policies in gem5, adding a partition ID to memory requests, and hosting ATP traffic models for all the challenge processing tasks outside of the CPU, challengers will have more tools at their disposal to explore and optimize their solutions.

[1] https://www.ecrts.org/industrial-challenge
[2] https://github.com/ecrtsorg/gem5/tree/stable/configs/example/arm/atp