Amrita University: Invitation for University Corporate Relations and Campus Hiring Initiatives

[Manjunatha K]

Dear students 

Please find Schedule for Sankalp Campus drive on 23rd Dec 2017. 2017 & 2018. batch. in Our campus 

Venue : Sudhamani hall 

Schedule 23rd Dec 2017

8:00am-9:00am - Registration ( on Spot registration)

9:00am - 9:30am - Pre-Placement Talk

9:30am - Written Test

12:30pm - Written Test Result and GD

1:00pm- Lunch

1:30pm Onward - Technical and HR Interviews

Thank you & regards,

Manjunatha k

Corporate & Industrial Relations

Amrita Vishwa Vidyapeetham

Bengaluru - 560035

Accept the challenges so that you can feel the exhilaration of victory.

                                                                                                                    - George S. Pattan

---

From: "Mukta M Joshi" 
To: "Sharatchandra Singh" <sharat...@blr.amrita.edu>
Cc: "sharat amritauniversity" <sharat.amri...@gmail.com>
Sent: Thursday, 14 December, 2017 11:44:55 AM
Subject: Re: Amrita University: Invitation for University Corporate Relations and Campus Hiring Initiatives

Dear Sharat,

Please find requirement for Sankalp Campus drive 2017 & 2018. Kindly share the eligible candidates list so that we will have both the process on the same day.

  Openings:

1. Graduate Engineers from the field of Electrical & Electronics, Electronics & Communications and Instrumentation

2. Post Graduate Engineers from the field of Electronics, VLSI

 

Eligibility: 70% aggregate or 7.75 CGPA 

 

Designation/Post – Design Engineer

The pay package (CTC) for the year 2018 joiners is 3.5 LPA.

 

Selected candidates will need to arrange for Bank Guarantee of Rs. 2 Lakhs for a period of 3Years 3Months. Background for Bank Guarantee will be explained to the candidates/students at the time of Pre-placement talk.

 Selection Procedure:

Sankalp’s selection procedure will have the following process in that order. Sequential clearing of each round leads to qualifying to the next round and Failing any round leads to elimination from selection. 

 1.       Written test

2.       Group Discussion

3.       Technical Interview

4.       HR interview

  The written test will be cover Technical (covering basic circuits with R, L, C, V, I, CMOS and Electronics) and Aptitude (Geometric & General).

 
The participants are expected to bring with them

• One Passport size photo of self
• One resume in hard copy (Name as per Aadhar Card)
• Pen, pencil, erasers to write the tests
• Scientific calculator’s are permitted but no sharing of the same will be entertained 
• Aadhar Card copy

Brief Job profile:

Sankalp works on deep sub-micron & ultra-deep sub--micron nodes in the areas of

· Analog layout – full chip, modules for a wide range of designs – floor planning, area challenges – RF, Power management, Data converters designs etc.

· IO designs – IO cells, interfaces with area, power & speed challenges – CMOS, LVDS IOs, USB etc.

· Modeling – PSPICE modeling of ICs – Modeling with extreme accuracy challenges.

· Digital cell libraries & digital backend – low-area, low-power libraries, digital implementation of modules – logic synthesis, place and route, clock tree synthesis, Static Timing Analysis, Timing closure, Design closure – challenges of shortest cycle time, lowest area etc.

 

At the end of the generic training modules, based on the needs, individuals will be assigned their specific areas of work, which will be based on the above. Sankalp has a formal Career Growth and Development (CGD) process, through which an individual’s career growth in the organization will be closely monitored and nurtured. 

 

Note: Kindly share the eligible candidates list by 19th Dec 2017.

For any clarification please revert back.

Regards,

Mukta.