Final Project - ALU simulation

[Elvis C. Justi Mota]

I still can't get the ALU RTL version to simulate with its gate version.
After synthesizing, the RTL code was divided into 7 separate modules.
Anybody else having the same experience?

Elvis

[Sam]

Yeah I had the same problem, I get the following files after trying to
synthesize the ALU file..

or1200_alu_DW01_ash_0.v
or1200_alu_DW01_add_0.v
or1200_alu_DW_rash_0.v
or1200_alu_DW01_ash_1.v
or1200_alu_DW01_sub_1.v
or1200_alu_DW01_add_1.v
or1200_alu_DW01_cmp6_0.v
or1200_alu.v

Any tips anyone??
-Sam

On Mar 14, 12:06 pm, "Elvis C. Justi Mota" <ejustim...@umail.ucsb.edu>
wrote:

[Bryce F]

Same experience.  I tested and they were not equivalent.  Got the following warnings using dc:

design compiler warnings and errors:
====================================

alu during reading:
Warning:  /fs/home1/student/b/bfurlong/HW5ECE156A/or1200_alu.v:209: signed to unsigned assignment occurs. (VER-318)
Warning:  /fs/home1/student/b/bfurlong/HW5ECE156A/or1200_alu.v:285: signed to unsigned conversion occurs. (VER-318)
Warning:  /fs/home1/student/b/bfurlong/HW5ECE156A/or1200_alu.v:287: signed to unsigned conversion occurs. (VER-318)
Warning:  /fs/home1/student/b/bfurlong/HW5ECE156A/or1200_alu.v:212: 'result_cust5' is being read, but does not appear in the sensitivity list of the block. (ELAB-292)
Warning:  /fs/home1/student/b/bfurlong/HW5ECE156A/or1200_alu.v:222: 'result_csum' is being read, but does not appear in the sensitivity list of the block. (ELAB-292)
Warning:  /fs/home1/student/b/bfurlong/HW5ECE156A/or1200_alu.v:255: 'flag' is being read, but does not appear in the sensitivity list of the block. (ELAB-292)

during compile:
Information: There are 3 potential problems in your design. Please run 'check_design' for more information. (LINT-99)

during check_design:
Warning: In design 'or1200_alu', a pin on submodule 'r139' is connected to logic
 1 or logic 0. (LINT-32)
   Pin 'DATA_TC' is connected to logic 0.
   Pin 'SH_TC' is connected to logic 0.
Warning: In design 'or1200_alu', the same net is connected to more than one pin
on submodule 'r139'. (LINT-33)
   Net 'n69' is connected to pins 'DATA_TC', 'SH_TC'.
Warning: In design 'or1200_alu', a pin on submodule 'add_181' is connected to lo
gic 1 or logic 0. (LINT-32)
   Pin 'A[32]' is connected to logic 0.
   Pin 'B[32]' is connected to logic 0.
   Pin 'CI' is connected to logic 0.
Warning: In design 'or1200_alu', the same net is connected to more than one pin
on submodule 'add_181'. (LINT-33)
   Net 'n71' is connected to pins 'A[32]', 'B[32]', 'CI'.
Warning: In design 'or1200_alu', a pin on submodule 'C598' is connected to logic
 1 or logic 0. (LINT-32)
   Pin 'DATA_TC' is connected to logic 0.
   Pin 'SH_TC' is connected to logic 0.
Warning: In design 'or1200_alu', the same net is connected to more than one pin
on submodule 'C598'. (LINT-33)
   Net 'n72' is connected to pins 'DATA_TC', 'SH_TC'.
Warning: In design 'or1200_alu', a pin on submodule 'C401' is connected to logic
 1 or logic 0. (LINT-32)
   Pin 'A[31]' is connected to logic 0.
   Pin 'A[30]' is connected to logic 0.
   Pin 'A[29]' is connected to logic 0.
   Pin 'A[28]' is connected to logic 0.
   Pin 'A[27]' is connected to logic 0.
   Pin 'A[26]' is connected to logic 0.
   Pin 'A[25]' is connected to logic 0.
   Pin 'A[24]' is connected to logic 0.
   Pin 'A[23]' is connected to logic 0.
   Pin 'A[22]' is connected to logic 0.
   Pin 'A[21]' is connected to logic 0.
   Pin 'A[20]' is connected to logic 0.
   Pin 'A[19]' is connected to logic 0.
   Pin 'A[18]' is connected to logic 0.
   Pin 'A[17]' is connected to logic 0.
   Pin 'A[16]' is connected to logic 0.
   Pin 'A[15]' is connected to logic 0.
   Pin 'A[14]' is connected to logic 0.
   Pin 'A[13]' is connected to logic 0.
   Pin 'A[12]' is connected to logic 0.
   Pin 'A[11]' is connected to logic 0.
   Pin 'A[10]' is connected to logic 0.
   Pin 'A[9]' is connected to logic 0.
   Pin 'A[8]' is connected to logic 0.
   Pin 'A[7]' is connected to logic 0.
   Pin 'A[6]' is connected to logic 0.
   Pin 'A[5]' is connected to logic 0.
   Pin 'A[4]' is connected to logic 0.
   Pin 'A[3]' is connected to logic 0.
   Pin 'A[2]' is connected to logic 0.
   Pin 'A[1]' is connected to logic 0.
   Pin 'A[0]' is connected to logic 1.
   Pin 'DATA_TC' is connected to logic 0.
   Pin 'SH_TC' is connected to logic 0.
Warning: In design 'or1200_alu', the same net is connected to more than one pin
on submodule 'C401'. (LINT-33)
   Net 'n67' is connected to pins 'A[31]', 'A[30]', 'A[29]', 'A[28]', 'A[27]', '
A[26]', 'A[25]', 'A[24]', 'A[23]', 'A[22]', 'A[21]', 'A[20]', 'A[19]', 'A[18]',
'A[17]', 'A[16]', 'A[15]', 'A[14]', 'A[13]', 'A[12]', 'A[11]', 'A[10]', 'A[9]',
'A[8]', 'A[7]', 'A[6]', 'A[5]', 'A[4]', 'A[3]', 'A[2]', 'A[1]'.
   Net 'n73' is connected to pins 'DATA_TC', 'SH_TC'.
Warning: In design 'or1200_alu', a pin on submodule 'sub_226' is connected to lo
gic 1 or logic 0. (LINT-32)
   Pin 'CI' is connected to logic 0.
Warning: In design 'or1200_alu', a pin on submodule 'add_1_root_add_183_2' is co
nnected to logic 1 or logic 0. (LINT-32)
   Pin 'A[32]' is connected to logic 0.
   Pin 'B[32]' is connected to logic 0.
Warning: In design 'or1200_alu', the same net is connected to more than one pin
on submodule 'add_1_root_add_183_2'. (LINT-33)
   Net 'n75' is connected to pins 'A[32]', 'B[32]'.
Warning: In design 'or1200_alu', a pin on submodule 'C670' is connected to logic
 1 or logic 0. (LINT-32)
   Pin 'TC' is connected to logic 0.
Warning: In design 'or1200_alu_DW01_ash_0', port 'DATA_TC' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_alu_DW01_ash_0', port 'SH_TC' is not connected to anynets. (LINT-28)
Warning: In design 'or1200_alu_DW01_add_0', port 'A[32]' is not connected to anynets. (LINT-28)
Warning: In design 'or1200_alu_DW01_add_0', port 'B[32]' is not connected to anynets. (LINT-28)
Warning: In design 'or1200_alu_DW01_add_0', port 'CI' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_alu_DW01_add_0', port 'CO' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_alu_DW_rash_0', port 'DATA_TC' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_alu_DW_rash_0', port 'SH_TC' is not connected to an nets. (LINT-28)
Warning: In design 'or1200_alu_DW01_ash_1', port 'A[31]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_alu_DW01_ash_1', port 'A[30]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_alu_DW01_ash_1', port 'A[29]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_alu_DW01_ash_1', port 'A[28]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_alu_DW01_ash_1', port 'A[27]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_alu_DW01_ash_1', port 'A[26]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_alu_DW01_ash_1', port 'A[25]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_alu_DW01_ash_1', port 'A[24]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_alu_DW01_ash_1', port 'A[23]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_alu_DW01_ash_1', port 'A[22]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_alu_DW01_ash_1', port 'A[21]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_alu_DW01_ash_1', port 'A[20]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_alu_DW01_ash_1', port 'A[19]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_alu_DW01_ash_1', port 'A[18]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_alu_DW01_ash_1', port 'A[17]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_alu_DW01_ash_1', port 'A[16]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_alu_DW01_ash_1', port 'A[15]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_alu_DW01_ash_1', port 'A[14]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_alu_DW01_ash_1', port 'A[13]' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_alu_DW01_ash_1', port 'A[12]' is not connected to anynets. (LINT-28)
Warning: In design 'or1200_alu_DW01_ash_1', port 'A[11]' is not connected to anynets. (LINT-28)
Warning: In design 'or1200_alu_DW01_ash_1', port 'A[10]' is not connected to anynets. (LINT-28)
Warning: In design 'or1200_alu_DW01_ash_1', port 'A[9]' is not connected to anynets. (LINT-28)
Warning: In design 'or1200_alu_DW01_ash_1', port 'A[8]' is not connected to anynets. (LINT-28)
Warning: In design 'or1200_alu_DW01_ash_1', port 'A[7]' is not connected to anynets. (LINT-28)
Warning: In design 'or1200_alu_DW01_ash_1', port 'A[6]' is not connected to anynets. (LINT-28)
Warning: In design 'or1200_alu_DW01_ash_1', port 'A[5]' is not connected to anynets. (LINT-28)
Warning: In design 'or1200_alu_DW01_ash_1', port 'A[4]' is not connected to anynets. (LINT-28)
Warning: In design 'or1200_alu_DW01_ash_1', port 'A[3]' is not connected to anynets. (LINT-28)
Warning: In design 'or1200_alu_DW01_ash_1', port 'A[2]' is not connected to anynets. (LINT-28)
Warning: In design 'or1200_alu_DW01_ash_1', port 'A[1]' is not connected to anynets. (LINT-28)
Warning: In design 'or1200_alu_DW01_ash_1', port 'A[0]' is not connected to anynets. (LINT-28)
Warning: In design 'or1200_alu_DW01_ash_1', port 'DATA_TC' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_alu_DW01_ash_1', port 'SH_TC' is not connected to anynets. (LINT-28)
Warning: In design 'or1200_alu_DW01_sub_1', port 'CI' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_alu_DW01_sub_1', port 'CO' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_alu_DW01_add_1', port 'A[32]' is not connected to anynets. (LINT-28)
Warning: In design 'or1200_alu_DW01_add_1', port 'B[32]' is not connected to anynets. (LINT-28)
Warning: In design 'or1200_alu_DW01_add_1', port 'CO' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_alu_DW01_cmp6_0', port 'TC' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_alu_DW01_cmp6_0', port 'EQ' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_alu_DW01_cmp6_0', port 'LE' is not connected to any nets. (LINT-28)
Warning: In design 'or1200_alu_DW01_cmp6_0', port 'GE' is not connected to any nets. (LINT-28)

write:
Writing verilog file '/fs/home1/student/b/bfurlong/HW5ECE156A/or1200_alu_DW01_as
h_0.v'.
Writing verilog file '/fs/home1/student/b/bfurlong/HW5ECE156A/or1200_alu_DW01_ad
d_0.v'.
Writing verilog file '/fs/home1/student/b/bfurlong/HW5ECE156A/or1200_alu_DW_rash
_0.v'.
Writing verilog file '/fs/home1/student/b/bfurlong/HW5ECE156A/or1200_alu_DW01_as
h_1.v'.
Warning: Verilog 'assign' or 'tran' statements are written out. (VO-4)
Writing verilog file '/fs/home1/student/b/bfurlong/HW5ECE156A/or1200_alu_DW01_su
b_1.v'.
Writing verilog file '/fs/home1/student/b/bfurlong/HW5ECE156A/or1200_alu_DW01_ad
d_1.v'.
Writing verilog file '/fs/home1/student/b/bfurlong/HW5ECE156A/or1200_alu_DW01_cm
p6_0.v'.
Writing verilog file '/fs/home1/student/b/bfurlong/HW5ECE156A/or1200_alu.v'.
Warning: Verilog 'assign' or 'tran' statements are written out. (VO-4)

---

From: Sam <smas...@gmail.com>
To: ECE 156B W10 <ece-15...@googlegroups.com>
Sent: Monday, March 15, 2010 1:52:59
Subject: Re: Final Project - ALU simulation

---

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[Michael Zimmer]

I got warnings and multiple modules as well, but it seems to work in simulation.

Michael