Decoding of arm64 ADD instruction

[Dmitry Vyukov]

Hi,

I am trying to decode this instruction using drdecode:

108e1f8: 4eb08607 add v7.4s, v16.4s, v16.4s

drdecode says it's:

add %q16 %q16 $0x02 -> %q7

Docs for ADD instruction say that if it has 3-rd source operand it's
shift/extend.
So I expect opnd_get_flags(instr_get_src(instr, 2)) to be either
DR_OPND_IS_SHIFT or DR_OPND_IS_EXTEND. But it's 0 in this case.

Is it an issue in drdecode (it shouldn't say there is 3-rd operand at all)?
Or should I just ignore the 3-rd operand with flags 0?
Or something else?

Thanks

[assad.hashm...@gmail.com]

> Docs for ADD instruction say that if it has 3-rd source operand it's shift/extend.

Which documentation are you looking at? Is it  XINST_CREATE_add_sll() ?
https://dynamorio.org/dr__ir__macros__aarch64_8h.html#a4e456d2d204fa85b0cbf4bf88bb432fb

The documentation for the instruction 'add v7.4s, v16.4s, v16.4s' is INSTR_CREATE_add_vector() at:
https://dynamorio.org/dr__ir__macros__aarch64_8h.html#ad6fa6d2ab7764783481efd209cf11b76

'add %q16 %q16 $0x02 -> %q7' is a vector add insruction which has 2 sources and a destination, all vector registers.
The third source parameter is the element size of the vectors, in this case $0x02, 32 bit single-word elements,  OPND_CREATE_SINGLE().

A common instruction like ADD has many variants, best looking through the documentation to find the right ones for your use-case.

Note that having a constant like $0x02 to represent vector element size is a legacy notation, which we hope to improve in future.
Our later implementation for AArch64 SVE is better, e.g.
04ad018b : add z11.s, z12.s, z13.s
is decoded as:
add    %z12.s %z13.s -> %z11.s