Question regarding AArch64 and lengthes in instructions

[Novasix3]

Hello,

I have a question regarding AArch64 : for some instructions (mostly the SIMD ones), there are sometime size associated with the operand.

Can DynamoRIO currently detect those ?

For instance, in the instruction : ld1r { v0.16b }, [x0]

We see that V0 (or in our case, Q0) is considered are 16 bytes, which is 128 bits. So is the "16b" part detected in some way ?

Moreover, is it detected in the case of multiple size for multiple operands ? "v0.2S v1.2S" -> can we detect both 2S.

Thanks for the answer :)

[Hendrik Greving]

The ARM people may comment on how the OPSZ enums are interpreted in ARM/AArch64. But generally you can query opnd_get_size() that gives you a OPSZ enum value of type opnd_size_t. The OPSZ type describes the operand's size. Hope this helps.

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[Novasix3]

Yes that technically gives me the right size, but how can I differenciate a "Q0.2S" from a "Q0.1D" or "Q0.4S" from "Q0.2D".

The sizes are the same, but the values I have to take into account are very different, and the AArch64 instructions don't make it easier, as for instance, FADD is the instruction to add floating scalar and vector, floats or doubles.

So there's no difference in the instruction other than the sizes of the different registers used.

Le mercredi 31 juillet 2019 16:40:33 UTC+2, Hendrik Greving a écrit :

The ARM people may comment on how the OPSZ enums are interpreted in ARM/AArch64. But generally you can query opnd_get_size() that gives you a OPSZ enum value of type opnd_size_t. The OPSZ type describes the operand's size. Hope this helps.

On Wed, Jul 31, 2019 at 3:13 AM Novasix3 <yoann...@netcourrier.com> wrote:

Hello,

I have a question regarding AArch64 : for some instructions (mostly the SIMD ones), there are sometime size associated with the operand.

Can DynamoRIO currently detect those ?

For instance, in the instruction : ld1r { v0.16b }, [x0]

We see that V0 (or in our case, Q0) is considered are 16 bytes, which is 128 bits. So is the "16b" part detected in some way ?

Moreover, is it detected in the case of multiple size for multiple operands ? "v0.2S v1.2S" -> can we detect both 2S.

Thanks for the answer :)

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[Assad Hashmi]

> Yes that technically gives me the right size, but how can I differenciate a "Q0.2S" from a "Q0.1D" or "Q0.4S" from "Q0.2D".

Currently we can't detect structured element sizes from the operand, just the flat element size based on:

DR_REG_Qn (128 bits)

DR_REG_Dn (64 bits)

DR_REG_Sn (32 bits)

DR_REG_Hn (16 bits)

DR_REG_Bn (8 bits)

SIMD support like this on AArch64 needs more work. 

[Hendrik Greving]

That's a question to the ARM guys on how to interpret the OPSZ or whether this info is lost. Assad, could you jump in?

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[Hendrik Greving]

Missed Assad's response.

@Novasix3 feel free to add support for this if you find this useful, it sounds to me like it would.

[Derek Bruening]

For x86 and for ARM (32-bit), the operand also does not distinguish by itself, but the opcodes are distinct.  Perhaps the AArch64 opcodes should be split to match.

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[Alireza Khadem]

Any updates on this? I need this feature.

[Derek Bruening]

For AArch64 I thought this was implemented as opnd_get_vector_element_size()?

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[Alireza Khadem]

I tested this. It always returns 0 (OPSZ_NA). It may be only implemented for SVE but I'm not sure.