How to run drcachesim with legacy memtrace for multiple core arch?

Lei Wang

unread,

Sep 13, 2022, 4:58:29 AM9/13/22

to DynamoRIO Users

Hi,

Recently I got some legacy single thread dynamorio offline trace. It looks like. aaa.<threadid>.memtrace.

I wanted to see the cache behaviors under multiple cores. So i created a 3 -level cache hierachy configuration file. The simulator outputs showed there are 8 cores. But all the events(hits, misses or compulsory hits/misses) were only showed on core 0. Furthermore the simulation result is the same as the single core(default conf). So I am not sure whether it is correct.

My dynamoRIO version: DynamoRIO-Linux-9.0.1

Platform: Intel Intel Core i9-10980XE

Host OS: Unbuntu 20.04

my command: drrun -t drcachesim -config_file cache_hierachy.conf -infile ./trace/1111.34562.memtrace.gz

BTW: I tried "-indir" with those legacy thread file. It didn't work. It showed the following error.

"Invalid header for input file #1"

Failed to read from trace.

Could someone help to take a look my question and give me some hints or suggestion?

Walter(Lei) Wang

Derek Bruening

unread,

Sep 13, 2022, 11:40:45 AM9/13/22

to Lei Wang, DynamoRIO Users

See the docs at https://dynamorio.org/sec_drcachesim_sim.html

By default, these cache and TLB simulators ignore that information and schedule threads to simulated cores in a static round-robin fashion with load balancing to fill in gaps with new threads after threads exit. The option "-cpu_scheduling" (see Simulator Parameters) can be used to instead map each physical cpu to a simulated core and use the recorded cpu that each segment of thread execution occurred on to schedule execution in a manner that more closely resembles the traced execution on the physical machine

Unless this thread moved around among cpus when traced, the current simulator code will keep it on one cpu. You would have to change the source code to artificially move it around, I assume pretending that there is some other load forcing the moves that is not itself being simulated?

--
You received this message because you are subscribed to the Google Groups "DynamoRIO Users" group.
To unsubscribe from this group and stop receiving emails from it, send an email to dynamorio-use...@googlegroups.com.
To view this discussion on the web visit https://groups.google.com/d/msgid/dynamorio-users/44235545-faad-416e-ad85-86f1ca095968n%40googlegroups.com.

Lei Wang

unread,

Sep 14, 2022, 5:30:49 AM9/14/22

to DynamoRIO Users

Thanks for your hits. I enabled cpu_scheduling switch in my cache hierarchy configuration. However I found the traces were only replayed on single core. All of thread were replayed on core 0. It seemed very strange. There were thousands of threads. It couldn't only record core 0 thread.

Any thoughts?

Derek Bruening

unread,

Sep 14, 2022, 5:00:36 PM9/14/22

to Lei Wang, DynamoRIO Users

In your first email you said " single thread" which is why I gave that reply about one thread. Now you are saying "thousands of threads". Maybe including the precise simulator output, which lists the number of threads on each core, or running "-simulator_type basic_counts" and showing the output with the thread count (and scheduling marker count), would help to clarify.

To view this discussion on the web visit https://groups.google.com/d/msgid/dynamorio-users/c6f9c754-ea89-4011-92a9-97cc86329e99n%40googlegroups.com.

Lei Wang

unread,

Sep 18, 2022, 10:28:33 PM9/18/22

to DynamoRIO Users

Maybe I made some confusion here. I had thousands of legacy thread trace files like xxxx.<tid>.memtrace.gz. This kind of file can't use -indir switch to load. It will report

"Invalid header for input file #1"

Failed to read from trace.

It can only be loaded by -infile switch. After simulation, I observed that it was only executed on core 0 no matter how many cores specified in the configuration file.

Here is my configuration file.

// Common params.

num_cores 64
line_size 64
cpu_scheduling true
sim_refs 549755813888
warmup_fraction 0.8

// Cache params.
C0L1I { // P0 L1 instruction cache
type instruction
core 0
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C0L1D { // P0 L1 data cache
type data
core 0
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C1L1I { // P0 L1 instruction cache
type instruction
core 1
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C1L1D { // P0 L1 data cache
type data
core 1
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C2L1I { // P0 L1 instruction cache
type instruction
core 2
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C2L1D { // P0 L1 data cache
type data
core 2
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C3L1I { // P0 L1 instruction cache
type instruction
core 3
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C3L1D { // P0 L1 data cache
type data
core 3
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C4L1I { // P0 L1 instruction cache
type instruction
core 4
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C4L1D { // P0 L1 data cache
type data
core 4
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C5L1I { // P0 L1 instruction cache
type instruction
core 5
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C5L1D { // P0 L1 data cache
type data
core 5
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C6L1I { // P0 L1 instruction cache
type instruction
core 6
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C6L1D { // P0 L1 data cache
type data
core 6
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C7L1I { // P0 L1 instruction cache
type instruction
core 7
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C7L1D { // P0 L1 data cache
type data
core 7
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C8L1I { // P0 L1 instruction cache
type instruction
core 8
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C8L1D { // P0 L1 data cache
type data
core 8
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C9L1I { // P0 L1 instruction cache
type instruction
core 9
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C9L1D { // P0 L1 data cache
type data
core 9
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C10L1I { // P0 L1 instruction cache
type instruction
core 10
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C10L1D { // P0 L1 data cache
type data
core 10
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C11L1I { // P0 L1 instruction cache
type instruction
core 11
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C11L1D { // P0 L1 data cache
type data
core 11
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C12L1I { // P0 L1 instruction cache
type instruction
core 12
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C12L1D { // P0 L1 data cache
type data
core 12
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C13L1I { // P0 L1 instruction cache
type instruction
core 13
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C13L1D { // P0 L1 data cache
type data
core 13
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C14L1I { // P0 L1 instruction cache
type instruction
core 14
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C14L1D { // P0 L1 data cache
type data
core 14
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C15L1I { // P0 L1 instruction cache
type instruction
core 15
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C15L1D { // P0 L1 data cache
type data
core 15
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C16L1I { // P0 L1 instruction cache
type instruction
core 16
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C16L1D { // P0 L1 data cache
type data
core 16
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C17L1I { // P0 L1 instruction cache
type instruction
core 17
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C17L1D { // P0 L1 data cache
type data
core 17
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C18L1I { // P0 L1 instruction cache
type instruction
core 18
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C18L1D { // P0 L1 data cache
type data
core 18
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C19L1I { // P0 L1 instruction cache
type instruction
core 19
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C19L1D { // P0 L1 data cache
type data
core 19
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C20L1I { // P0 L1 instruction cache
type instruction
core 20
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C20L1D { // P0 L1 data cache
type data
core 20
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C21L1I { // P0 L1 instruction cache
type instruction
core 21
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C21L1D { // P0 L1 data cache
type data
core 21
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C22L1I { // P0 L1 instruction cache
type instruction
core 22
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C22L1D { // P0 L1 data cache
type data
core 22
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C23L1I { // P0 L1 instruction cache
type instruction
core 23
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C23L1D { // P0 L1 data cache
type data
core 23
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C24L1I { // P0 L1 instruction cache
type instruction
core 24
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C24L1D { // P0 L1 data cache
type data
core 24
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C25L1I { // P0 L1 instruction cache
type instruction
core 25
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C25L1D { // P0 L1 data cache
type data
core 25
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C26L1I { // P0 L1 instruction cache
type instruction
core 26
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C26L1D { // P0 L1 data cache
type data
core 26
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C27L1I { // P0 L1 instruction cache
type instruction
core 27
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C27L1D { // P0 L1 data cache
type data
core 27
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C28L1I { // P0 L1 instruction cache
type instruction
core 28
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C28L1D { // P0 L1 data cache
type data
core 28
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C29L1I { // P0 L1 instruction cache
type instruction
core 29
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C29L1D { // P0 L1 data cache
type data
core 29
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C30L1I { // P0 L1 instruction cache
type instruction
core 30
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C30L1D { // P0 L1 data cache
type data
core 30
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C31L1I { // P0 L1 instruction cache
type instruction
core 31
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C31L1D { // P0 L1 data cache
type data
core 31
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C32L1I { // P0 L1 instruction cache
type instruction
core 32
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C32L1D { // P0 L1 data cache
type data
core 32
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C33L1I { // P0 L1 instruction cache
type instruction
core 33
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C33L1D { // P0 L1 data cache
type data
core 33
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C34L1I { // P0 L1 instruction cache
type instruction
core 34
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C34L1D { // P0 L1 data cache
type data
core 34
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C35L1I { // P0 L1 instruction cache
type instruction
core 35
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C35L1D { // P0 L1 data cache
type data
core 35
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C36L1I { // P0 L1 instruction cache
type instruction
core 36
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C36L1D { // P0 L1 data cache
type data
core 36
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C37L1I { // P0 L1 instruction cache
type instruction
core 37
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C37L1D { // P0 L1 data cache
type data
core 37
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C38L1I { // P0 L1 instruction cache
type instruction
core 38
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C38L1D { // P0 L1 data cache
type data
core 38
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C39L1I { // P0 L1 instruction cache
type instruction
core 39
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C39L1D { // P0 L1 data cache
type data
core 39
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C40L1I { // P0 L1 instruction cache
type instruction
core 40
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C40L1D { // P0 L1 data cache
type data
core 40
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C41L1I { // P0 L1 instruction cache
type instruction
core 41
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C41L1D { // P0 L1 data cache
type data
core 41
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C42L1I { // P0 L1 instruction cache
type instruction
core 42
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C42L1D { // P0 L1 data cache
type data
core 42
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C43L1I { // P0 L1 instruction cache
type instruction
core 43
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C43L1D { // P0 L1 data cache
type data
core 43
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C44L1I { // P0 L1 instruction cache
type instruction
core 44
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C44L1D { // P0 L1 data cache
type data
core 44
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C45L1I { // P0 L1 instruction cache
type instruction
core 45
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C45L1D { // P0 L1 data cache
type data
core 45
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C46L1I { // P0 L1 instruction cache
type instruction
core 46
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C46L1D { // P0 L1 data cache
type data
core 46
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C47L1I { // P0 L1 instruction cache
type instruction
core 47
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C47L1D { // P0 L1 data cache
type data
core 47
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C48L1I { // P0 L1 instruction cache
type instruction
core 48
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C48L1D { // P0 L1 data cache
type data
core 48
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C49L1I { // P0 L1 instruction cache
type instruction
core 49
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C49L1D { // P0 L1 data cache
type data
core 49
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C50L1I { // P0 L1 instruction cache
type instruction
core 50
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C50L1D { // P0 L1 data cache
type data
core 50
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C51L1I { // P0 L1 instruction cache
type instruction
core 51
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C51L1D { // P0 L1 data cache
type data
core 51
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C52L1I { // P0 L1 instruction cache
type instruction
core 52
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C52L1D { // P0 L1 data cache
type data
core 52
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C53L1I { // P0 L1 instruction cache
type instruction
core 53
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C53L1D { // P0 L1 data cache
type data
core 53
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C54L1I { // P0 L1 instruction cache
type instruction
core 54
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C54L1D { // P0 L1 data cache
type data
core 54
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C55L1I { // P0 L1 instruction cache
type instruction
core 55
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C55L1D { // P0 L1 data cache
type data
core 55
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C56L1I { // P0 L1 instruction cache
type instruction
core 56
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C56L1D { // P0 L1 data cache
type data
core 56
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C57L1I { // P0 L1 instruction cache
type instruction
core 57
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C57L1D { // P0 L1 data cache
type data
core 57
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C58L1I { // P0 L1 instruction cache
type instruction
core 58
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C58L1D { // P0 L1 data cache
type data
core 58
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C59L1I { // P0 L1 instruction cache
type instruction
core 59
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C59L1D { // P0 L1 data cache
type data
core 59
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C60L1I { // P0 L1 instruction cache
type instruction
core 60
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C60L1D { // P0 L1 data cache
type data
core 60
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C61L1I { // P0 L1 instruction cache
type instruction
core 61
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C61L1D { // P0 L1 data cache
type data
core 61
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C62L1I { // P0 L1 instruction cache
type instruction
core 62
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C62L1D { // P0 L1 data cache
type data
core 62
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

// Cache params.
C63L1I { // P0 L1 instruction cache
type instruction
core 63
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}
C63L1D { // P0 L1 data cache
type data
core 63
size 64k // 64K
assoc 8
parent L2
replace_policy LRU
}

L2 { // P0 L2 unified cache
size 1m
assoc 16
inclusive true
parent LL
replace_policy LRU
}
LL { // LLC
size 2m
assoc 16
inclusive true
parent memory
replace_policy LRU
miss_file misses.txt
}

The simulation output screen shot is attached. It seemed that all the instructions were replayed on core 0.

multcore.PNG

Derek Bruening

unread,

Sep 19, 2022, 12:36:57 PM9/19/22

to Lei Wang, DynamoRIO Users

But if your trace file contains one software thread, and you only passed that one file to the simulator, you would expect it to run on a single core for the reason in my very first reply. It is unrelated to the simulator config file.

It sounds like the issue is all about -indir not taking all these files and preventing simulating all the threads at once. Please, include the exact command line and output with -verbose 4 that leads to the header error.

When you say "legacy thread trace files" what does that mean? There was a format change back in 2018 which switched from a multi-thread-interleaved-in-one-file format to a separate file per software thread. If this is from after that switch (I assume so from your description), what is making it "legacy"? What does the header entry look like: what is the version number? Run the view tool and paste the first few lines here, or paste the first few binary lines using od or hexdump as detailed at

https://dynamorio.org/page_debug_memtrace.html#autotoc_md134.

To view this discussion on the web visit https://groups.google.com/d/msgid/dynamorio-users/85208a40-c1b1-4bba-aae0-2d377ef5daacn%40googlegroups.com.

Lei Wang

unread,

Sep 20, 2022, 6:27:25 AM9/20/22

to DynamoRIO Users

I think I found the problem. This issue is caused by the file filter of the dynamorio. If you want to use -indir, the folder should only contain memtrace files. It shouldn't contain any other files or even a directory. The current get file won't filter the non trace files and folders.

If I can keep the folder only contains memtrace file, the simulation works well.

Another small problem, I need to unzip all gz file to memtrace. If the memtrace is compressed, the simulation can't load them either.

Derek Bruening

unread,

Sep 20, 2022, 11:03:58 AM9/20/22

to Lei Wang, DynamoRIO Users

On Tue, Sep 20, 2022 at 6:27 AM Lei Wang <eshar...@gmail.com> wrote:

I think I found the problem. This issue is caused by the file filter of the dynamorio. If you want to use -indir, the folder should only contain memtrace files. It shouldn't contain any other files or even a directory. The current get file won't filter the non trace files and folders.

Yes, see my reply on the other thread https://groups.google.com/g/DynamoRIO-Users/c/DLLeSeXH8ng/m/54jbAgIaAwAJ. The error will at least list the non-memtrace file by name.

If I can keep the folder only contains memtrace file, the simulation works well.

Another small problem, I need to unzip all gz file to memtrace. If the memtrace is compressed, the simulation can't load them either.

gzipped trace files work fine if DR is built with zlib. Are you using a custom-built DR and you didn't have the zlib dev library installed when you built?

To view this discussion on the web visit https://groups.google.com/d/msgid/dynamorio-users/3b46f156-e4ec-4edc-bdaa-be677fd28822n%40googlegroups.com.

Lei Wang

unread,

Sep 21, 2022, 5:32:07 AM9/21/22

to DynamoRIO Users

I find another problem. If you want to use -indir, you need to enlarge the open files limit of linux. I found -indir worked with delta. But it didn't work with charlie and others. The only difference is the trace file number. I checked the ulimit which showed that the default maximum open files was 1024. It is smaller than the trace files number of the charlie. After I enlarge the maximum open number to 8192, it worked well under ubuntu.

Derek Bruening

unread,

Sep 22, 2022, 9:00:59 AM9/22/22

to Lei Wang, DynamoRIO Users

Interesting, so this likely explains all the errors about being unable to open the nth trace file: an rlimit was hit. Unfortunately rlimits in general are hard to diagnose but maybe the error message could mention it as something to check.

To view this discussion on the web visit https://groups.google.com/d/msgid/dynamorio-users/e06ef72e-bbc5-4006-a5f4-9e9399a718e6n%40googlegroups.com.

Reply all

Reply to author

Forward