Fwd: Verilog Syntax

[Paul Campbell]

Martin asked me to share this with you - a gentle this document introduces
some stuff that is not synthesisable, I'd recommend that people not use verilog
syntax that wasn't introduced in last week's talk, which is available here:

http://www.taniwha.com/~paul/ttcourse.html

Remember that you have homework, I'm asking you to write some simple verilog
that we're going to load into an FPGA on Thursday. Also please try and load
Vivado onto your laptop, if you can't we'll share mine

Paul

---------- Forwarded Message ----------

Subject: Verilog Syntax
Date: Tuesday, 14 March 2023, 10:02:08 AM NZDT
From: Martin Hohmann-Marriott <martin.hohm...@united-scientists.org>
To: Paul Campbell <pa...@taniwha.com>




Hi Paul

I am working on my homework ... and its a bit of a steep learning curve.
I came across this document that I found very helpful.
https://www.iitg.ac.in/hemangee/cs224_2020/verilog2.pdf
May be worth sharing with people like me in the course?

Cheers, Martin
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