Tiny Tapeout course week 2

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Paul Campbell

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Mar 16, 2023, 4:32:31 PM3/16/23
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Thanks for those who showed up this week, for those who were unable to show up
you can find the talk here:

http://www.taniwha.com/~paul/vcourse2/index.html

This was essentially a gentle overview of synthesis and place and route
followed by a walk through of setting up Vivado to load some simple verilog
into an FPGA (it's a bit cryptic at the end unless you have Vivado open in
front of you).

If you missed out I'll be happy to walk you through after the main course is
done, I also have an FPGA dev board that I'm happy to let people take home for
a week to play with.

You do not have to have done the 2nd class to do the final one (the actual tiny
tapeout). So if you are planning on coming a quick reminder of your homework,
please:

- create a github account if you don't already have one, they are free
- create some simple verilog to start with, TT allows you 8 inputs and 8
outputs, 2 of the inputs are hardwired as clock and reset, you should start
with this:

module my_design (input [7:0] io_in, output [7:0] io_out);

wire clk = io_in[0];
wire reset = io_in[1];

....

it doesn't have to be your final design for Tiny Tapeout, just a place to start

Paul


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