Tiny Tapeout 4 open for submissions

[Paul Campbell]

TT4 is open for submissions https://tinytapeout.com/ - it will close in early
September.

Prices/etc are the same as before (US$50/slot), I've also submitted and
ordered a PCB so you're welcome to borrow my board if you submit.

The main differences this time are that you can now have multiple slot
submissions (mine is 1x2 slots), and the interface is wider and far faster
(~20nS to the pads rather than a multi-clock scan chain) - 50MHz designed are
expected to be doable.

Previously there were 8 inputs and 8 outputs per design and 2 of the inputs
were assigned to clock and reset. This time there are dedicated clock and
reset_n pins, 8 inputs, 8 outputs, and 8 individually bi-directional pins.

The new top level looks like this:

module tt_um_vc_cpu (
input wire [7:0] ui_in, // Dedicated inputs - connected to the input
switches
output wire [7:0] uo_out, // Dedicated outputs - connected to the 7
segment display
input wire [7:0] uio_in, // IOs: Bidirectional Input path
output wire [7:0] uio_out, // IOs: Bidirectional Output path
output wire [7:0] uio_oe, // IOs: Bidirectional Enable path (active
high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);

The 8-bit bi-directional bus is uio_in/uio_out/uio_oe - output pad X is
driven if uio_oe[X] is 1. All unused outputs should be driven by something
(just do something like "assign uio_oe=0;assign uio_out=0;" etc if you are not
using them). Also note that the reset is inverted from last time and
asynchronous, I recommend doing this:

reg r_reset;
always @(posedge clk)
r_reset <= ~rst_n|~ena;
assign reset = r_reset;

and use reset as you did before.

Even if you have a design you should start again by forking:
https://github.com/TinyTapeout/tt04-verilog-demo

The way that releases work has changed, previously if you had signed up they
would refresh your build automatically, now you have to explicitly request it
to pull your changes

You can find my design (a RISC-V C subset CPU) here
https://app.tinytapeout.com/projects/13

As last time feel free to ask me an y question s, if you weren't around for
the last round of TT talks I'm happy to take you through them on Thursday
nights

Paul