Test-Bench

[Prashanth Anil Mascarenhas]

Hi Niraj, Rajesh,

 As discussed yesterday, We created the Test-bench for:

1.pMOS Ids

>Varying Width

>Varying Length

2.nMOS Ids
>Varying Width
>Varying Length

3.Inverter

>Leakage

Can we have discussion on the same?.

Are we going in right direction?.

What about the weekly plan on Lilliput project? and also the MOM template.

Thank you.

--
Regards,
Prashanth Anil Mascarenhas,
+918904231492,
Sankalp Semiconductor Pvt Ltd.

[Sushant Seetaram Hedge]

Hi Rajesh,
Please let us know when will you take the review for the
testbench we created.
Thank you.

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Regards,
Sushant Hegde
Contact-7411499789
Sankalp Semiconductor Pvt. Ltd.

[Avinash Venigalla]

Hi Rajesh,Niraj

 We have done various simulations pertaining to the leakage and capacitance.We also studied the variation of the leakage and capacitances with length and the width .We thought that now if the cell size was got decided, then we can go with the device optimization and start with the standard cells with this knowledge.The plan we thought is 

1.First we start with the 1x inverter  - we run the simulation for getting the width and length of the pmos and nmos involving low leakage and high speed.

2. Once it was done then we go with the other cells with different drive strength.

Please let us know if any issues and let us know that whether these simulations were required or not.

Avinash Venigalla,
+919620394049,
Sankalp Semiconductor Pvt. Ltd.