The Simulation is Run for Process=FF, Temp=-40C, C=10f/40f F, Rise delay/Fall delay=100p/700p s, VDD=0.99V.
The delay is looked from Fourth Block O/P to First Block I/P and Fourth Block I/P to Fourth Block O/P.
The Schematic picture is attached along with this mail.
Since time was bit tight, analysis on data will be continued tomorrow. Please let me know whether the simulated data is correct or any changes is required or not.
Tomorrow will be working on :
1. Simulation on Boolean function with doubling nMOS width of two transistors.
2.Comparing the results.
Thank you.
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Regards,
Prashanth Anil Mascarenhas,
+918904231492,
Sankalp Semiconductor Pvt Ltd.