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Prashanth Anil Mascarenhas

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Feb 5, 2013, 9:04:21 AM2/5/13
to Rajesh Rebba, Sivakumar PS, Niraj Kumar Mahapatro, Digita...@googlegroups.com
Hi all,
    As discussed in the pre-lunch, I had run simulation on Boolean Function Y=(AB+C)!.

Since it was found that by shorting A and B to 0 (Or any one to zero) , we can make the schematic behave as Inverter. The simulation is done according to this.

For both A and B input high, output is zero always, For this we cannot calculate the delay and all so this condition is neglected.

The Simulation is Run for Process=FF, Temp=-40C, C=10f/40f F, Rise delay/Fall delay=100p/700p s, VDD=0.99V.

The delay is looked from Fourth Block O/P to First Block I/P and Fourth Block I/P to Fourth Block O/P.

The Schematic picture is attached along with this mail.

Since time was bit tight, analysis on data will be continued tomorrow. Please let me know whether the simulated data is correct or any changes is required or not.

Tomorrow will be working on :
1. Simulation on Boolean function with doubling nMOS width of two transistors.
2.Comparing the results.

The Result is Shared in Lilliput Project Excel Sheet. The Link is given below:
https://docs.google.com/a/sankalpsemi.com/spreadsheet/ccc?key=0An2k5ERxOhlzdGFWTGRuU25tbHRUczF0cVFfLWxKakE#gid=24

Thank you.
--
Regards,
Prashanth Anil Mascarenhas,
+918904231492,
Sankalp Semiconductor Pvt Ltd.
Boo.gif
Boolean.gif

Prashanth Anil Mascarenhas

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Feb 6, 2013, 2:19:40 AM2/6/13
to Rajesh Rebba, Sivakumar PS, Niraj Kumar Mahapatro, Digita...@googlegroups.com
Hi Rajesh, Siva,

I have run simulation on the Boolean function Y=(A+BC)! .
The simulation were done by setting:
1.All the nMOS width as same.(Keeping the same resistance in individual transistors)
2.The series nMOS (two transistors) width has been doubled for each variations. Keeping the series resistance same as that of NOR gate.

Analysis:
  • There is no much difference in the two simulated values.
  • The beta value varies in between 1.12 - 1.26 .
  • The delay time is minimum for length minimum.
  • Comparatively the value when nMOS width is doubled is having a slight large delay compared to first case.

The results have been updated in Lilliput project Excel sheet. The link is given below:
https://docs.google.com/a/sankalpsemi.com/spreadsheet/ccc?key=0An2k5ERxOhlzdGFWTGRuU25tbHRUczF0cVFfLWxKakE#gid=24


Thank you

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