Fwd: FW: EMPLOYEE REFERRAL

[Malatesh Goudar]

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From: pradeep satwic <pradeep...@gmail.com>
Date: Mon, Sep 28, 2015 at 9:51 PM
Subject: Fwd: FW: EMPLOYEE REFERRAL
To: "Ravi H G (RBEI/EEP1)" <Ravi.H...@in.bosch.com>, Harish Kumar SG <hari...@gmail.com>, raghavendra tm <ragh...@gmail.com>, Malatesh Goudar <mygo...@gmail.com>, lokesh L <lokes...@gmail.com>, Santhosh Nataraj <santhos...@gmail.com>

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From: "NAGARAJ S J" <canag...@gmail.com>
Date: Sep 28, 2015 7:18 PM
Subject: Fwd: FW: EMPLOYEE REFERRAL
To: "pradeep satwic" <pradeep...@gmail.com>, "Uma Dakshinamurthy" <umam...@gmail.com>, "Ranjith Dhananjaya" <ranji...@gmail.com>, "Raghavendra S G" <raghaven...@gmail.com>, "prasad t m" <prasadm...@gmail.com>
Cc:

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From: Jayakumar Nagaraj <nagaraj.ja...@altran.com>
Date: Mon, Sep 28, 2015 at 7:15 PM
Subject: FW: EMPLOYEE REFERRAL
To: "canag...@gmail.com" <canag...@gmail.com>

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From: Roy Neelam
Sent: 28 September 2015 08:22:19
To: ML-IN-ALTIND-ALLEMPLOYEE; ML-IN-ASI-ALLEMPLOYEE
Cc: Gangavaram Rekha
Subject: EMPLOYEE REFERRAL

Hi All,

 

Below are the Openings in Hardware Division for Bangalore Location. Please send your referral profiles to rekha.gang...@altran.com

 

 

 

Job ID	Area	Experience	Skills
1	DFT Engineer	3-8 years	-          Chip-level DFT insertion with sound knowledge of scan compression, MBIST & JTAG techniques -          Should have good post silicon DFT bringup and debug experience -          Hands on in multi vendor DFT tools -          Create test plan for complex ASICs and drive the DFT implemetation & verification -          Ability to guide people, multiplex many issues and set priorities -          Good communication and leadership skills
2	RTL	3-10Years	-          RTL IP assembly knowledge. Understanding of IPXACT a plus. -          Hands on experience of coding in Verilog and VHDL. -          Understanding of Power Intent, Power estimation and checks. -          Experience of Design rule checks and Clock domain crossing checks using Spyglass or similar tool. -          Specification writing. -          IP RTL development experience. -          Good knowledge of version control tools like Clearcase and Design sync.
3	FPGA	3-10Years	-          Expertise in FPGA/SOPC Implementations  -           End-to-End FPGA/System Development  -          Expertise in Xilinx/Altera FPGA Implementation flow -           Logic Estimation -           FPGA Selection
4	PD Engineer	3-8+years	-          Proven experience of complex SOC in a position of accountability and not just task runner -          Thorough understanding and knowledge of the entire Back end flow -          Should have work experience in the latest technology nodes, 45nm at least if not 32/28nm -          Should be familiar with low-power design and their impact on Back end flow -          Good communication and managerial skills, should be able to drive the team -          Ready for challenges and should be open to constraints and advices
5	Verification Engineer	3-8 +years	-          Lead a team of 10 people for verification closure at SoC and block level. -          Guide team to create verification plans at module and chip level for complex SOC`s. -          Should have excellent communication and managerial skills -          Should have basic knowledge of other domains like Design, DFT and Physical design -          Should have deep knowledge and experience on starting from scratch and building verification environment design and environment. -          Should have good understanding of specman.
6	Senior Analog Layout Engineer	5-10 years	-          Candidate will be responsible for doing hands on  full custom analog/mixed signal /RF layouts on cutting edge technology and will be layout lead. -          Bachelors or above on Electronics, Communications or Microelectronics Engineering. Strong skills on CMOS analog/mixed signal/RF Layout. -          Good understanding of devices and process technology. Expertise on matching, parasitic reduction,  ESD, DFM etc. -          Proficiency in use of EDA tools for full custom layout and post-layout verification DRC/LVS/DFM etc. -          Experience on full chip layout & verification,  Data converters, high speed Phy’s & PM layouts are preferable. -          Knowledge of perl/shell/skill scripting languages is an added advantage. -          Good communication and leadership skills.

 

7	STA Engineer	3-12 years	-          Should have good timing concepts and able to close timing of Block/SoC independently. -          Should have hands on experience in constraint generation -          Hands on experience in Logical synthesis -          Knowledge in Formal Verification -          Should able to generate and implement functional Ecos -          Should have experience in Pre-layout and Post layout timing analysis -          Hands on experience in crosstalk timing closure. -          Knowledge in Path based analysis, AOCV, DMSA is a plus. -          Knowledge in complete physical Design flow is a plus.
8	Memory design & Characterization	3-7 years	-          The candidate will be working in memory design and characterization. -          As part of the design, the candidate would be involved in SRAM or ROM memory design either from scratch or as part of optimization of the existing design. -          The candidate would be working on design robustness analysis using appropriate simulation tools. -          He will also be working on characterization of the memory and generating final timing models for compiler or for memory instance. -          Candidate will work on design and characterization as individual contributor as well as working with the team.
9	RF Layout	3-8 years	-          Must have minimum 3+ years RF layout Experience with blocks like LAN, Mixer, VCO, PA, PLL, LO distribution blocks etc. -          Work experience on WLAN & BT chip sets. -          Knowledge on RF component layout like Inductor, Varactor diodes and Flux capacitors -          Experience on 40nm or lower technology node is necessary -          Experience with Cadence and Mentor layout tools (Virtuoso XL, Assura, Calibre) is required -          Candidate will interact closely with the circuit designers, must be able to work in a multi-site environment, have good   communications skills.
10	AMS Verification	3-8 years	-          Create AMS verification setup of complex mixed signal IP -          Verilog-A model creation -          Understand UVM environment and integrate AMS verification -          Execute verification tasks. -          Minimum of 3 years in AMS verification -          Clear understanding of  best verification practices -          Expertise with verilogA, Verilog, scripting language (PERL preferred) and SPICE -          UVM understanding -          Experience with Signal and Power Integrity
11	IO Cell Design	3-8 years	-          3+years experience in hands-on design of IO cells -          Experience in deep submicron CMOS technology nodes (65nm to 28nm) -          Understanding an IO specification and deriving block level specifications from the same -          Coming up with IO and block level architectures -          Design of actual circuit blocks and simulation/verification of the same -          Guiding the layout team and/or doing actual layout of the IO cell
12	Standard cell Characterization	2-5 years	-          3 or more year of exp in std cell/custom layout -          Should have worked on virtuoso and caliber for verifications.
13	Senior Design Engineer,Layout	2-5 years	-          Candidate must have experience in layout design of memory leaf cells and at top level of memories should have worked on  45nm / 28nm/16nm process technologies. He/She must have good understanding of physical verification checks. DRC, LVS, ERC and reliability checks . IR and EM. -          He/She must have worked on cadence tools for layout design and Cadence/Mentor/Synopsys tools for physical verification checks.    -          He/She must have good understanding of Basics of CMOS circuits.  Basic knowledge of skill or any compiler related language would be required.
14	Lead Design Engineer, Layout	5-10yrs	-          Bachelor or Master’s in (Micro) Electronics plus 7+ years of experience in physical design (28nm,20nm and beyond) -          Hands on experience in Synthesis and/or Custom design in 1 GHz-3Ghz frequency o    Including exposure to Design Compiler, IC Compiler, Nano-Route, Z-Route etc) -          Working knowledge of Timing Analysis, physical verification, signal integrity issues o    Including Primetime STA, Calibre DRC/LV,  EM/IR analysis using Apache Redhawk etc -          Exposure to Digital Circuit Design -          Exposure to SRAM memory design is desirable -          Leadership ·           Ability to lead / mentor a group of 4-8 engineers ·           Strong domain expertise in one or more areas of physical design ·           PERL, Unix & TCL coding skills ·           Ability to drive new methodology and competency development to improve power, frequency and performance

 

 

 

Thanks & Regards,

Neelam Roy

Recruitment Manager

Altran India

 

ALTRAN TECHNOLOGIES INDIA PVT LTD.

RMZ Ecospace

2^nd floor, Block 9B,

Pritech Park SEZ,

Bellandur Village, Varthur Hobli,

Bangalore- 560037

Tel. : + 91 80 79 40 86 00
Mob. : + 91 98 45 01 26 81
neela...@altran.com

www.altran.com

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