Re: Reqs in Qualcomm

[Venkatesh Ragala]

+More Folks.

Dear Buddies,

Please see the mail below. If you're looking out, please contact Rajesh directly @ his e-mail.

Thanks,

Venky

On Thu, Jun 30, 2016 at 8:53 AM, venkata rajesh <mvra...@gmail.com> wrote:

Hi:

My team is expanding and have several reqs for ASIC Design and Verification all based in San Jose. If you are interested, Pls. forward your resume to me. Thanks.

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**************************************************
Thanks & Regards
Venkata Rajesh Mekala
Webpage: http://mvrajesh1.googlepages.com/main-home
Email: mvra...@gmail.com
Phone: 806-418-0363

**************************************************

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[Venkatesh Ragala]

Rajesh,

Please send the job descriptions for the positions that you sent.

Some people are looking forward to them.

Thanks,

Venky

[venkata rajesh]

I received ~ 20 resumes, forwarded all of them to the director. I guess they are busy in screening resumes/travelling. Sorry if you do not happen to get a call until now.

Below are Job IDs:

E1944906

E1944609

E1944604

E1944606 

E1944645

Location		California - San Jose
Job Overview		Qualcomm QTI Digital ASIC Design Team is currently seeking candidates with chip design and I/P integration experience to be involved with SoC creation for advanced multi-CPU core designs. The Design/SoC Integration Engineer will work with internal and external I/P blocks, subsystems and RTL logic - with responsibilities like logic design, integration and documentation including functional specifications and test plans Responsibilities Logic design and RTL development Leverage strong domain knowledge of PCIE Express and develop effective design blocks targeted towards data server applications Perform integration of multiple PCIE express IP cores along with the PHY interface into SoC designs Work directly with core/block developers for complete integration parameters and requirements Work directly with verification team, assisting with RTL and gate-level simulation debug Work with Physical design team for complete design performance achievement including timing closure assistance Assist in silicon bring-up and debug Create SoC documentation including address and interrupt maps, block diagrams, complete low-level design descriptions and chip specification
Minimum Qualifications		Strong domain knowledge of PCIE express protocol is a must Experience in Logic Design, Verilog & SystemVerilog RTL, verification, synthesis, LINT and static timing analysis, clock domain crossing techniques/implementation Working knowledge of PCIE express Serdes and PCS layers Working knowledge in one or more of the following: C, C++, TCL or Perl. Strong fundamental knowledge of high performance processors and large complex SOCs Solid background in scripting for automation of design methodologies & flows Detail oriented with strong organizational, problem solving, and communication skills (both written and oral) Strong understanding of chip integration procedures, methodologies & flows Ability to work in a team environment
Preferred Qualifications		Direct and relevant experience with multi-CPU core SOC solutions ARMv8 processor architecture understanding and knowledge Working knowledge of I/O Virtualization Broad experience in SoC development from design concept through silicon bring-up Bus Protocol experience for the following: Coherent Interconnects, AHB, AXI, I2C, SPI, SMBus, JTAG Formal Verification

[Venkatesh Ragala]

Wow!!  Enjoy the referral bonus man!!!😀

[venkata rajesh]

Qualcomm doesn't have any referral bonus, just wanted someone we know