Re: dff

[Harinath Renukamurthy]

Hi Shivangi,
After I left the class yesterday I wanted to recheck the biasing of Transmission Gate transistors. Your mail now confirms that. I will explain this next week.

I am happy to hear that the flop is working fine now :-)

Best Regards,
Harinath

On Fri, Feb 10, 2012 at 5:20 PM, Shivangi Sharma <shivang...@snksemi.com> wrote:

Hi Sir,

 We got dff o/p ,the mistake was we removed body to vdd and vss
connection and connect them to source of the transistors  ,but i didnt
understand the concept .


Thanks & Regards,
Shivangi Sharma

[Sharif H N]

Hi sir Good morning,
The email that you were sending to shivangi came to me.
I also got that dff's output yesterday but I'm not clear about the
working concept.

--
With regards....
***Sharif H Nadaf*
Fellow of SUSANDHI SANKALP
Deshpande foundation
DCSE Building BVB Hubli
Karnataka India

[Sharif H N]

Hi sir Good morning,
The email that you were sending to shivangi came to me.
I also got that dff's output yesterday but I'm not clear about the
working concept.

On 2/11/12, Harinath Renukamurthy <harin...@sankalpsemi.com> wrote: