Question on Nand/Nor Gates
Harinath Renukamurthy
Here is a question on NAND and NOR gate design.
Look at the table. Why is the following happening? How do you get a balanced delay for a NOR gate?
NAND
Wp Wn TPLH TPHL
0.6 0.6 34.77 33.597 <----- delay is balanced
1.2 0.6 19.069 55.83 <------ delay is not balanced
NOR
Wp Wn TPLH TPHL
0.6 0.6 12.953 81.583 <------ delay is not balanced
1.2 0.6 ?? ?? <------ find out
The above sizing experiment was done by Akshata and Savitri on their own. Keep it up!
Hi Yokeswaran,
You too have to complete the assignments related to CMOS gates by taking help from Sonam and others.
Best Regards,
Harinath
Sonam Agrawal
I am getting these values.
I've taken WRT output rising and falling.
*NOR*
> Wp Wn TPLH TPHL
> 0.6 0.6 107.90 15.96
1.2 0.6 82.16 5.75
On 2/14/12, Harinath Renukamurthy <harin...@sankalpsemi.com> wrote:
> Dear All,
> Here is a question on NAND and NOR gate design.
>
> Look at the table. Why is the following happening? How do you get a
> balanced delay for a NOR gate?
> *
>
> NAND*
> Wp Wn TPLH TPHL
> 0.6 0.6 34.77 33.597 <----- delay is balanced
> 1.2 0.6 19.069 55.83 <------ delay is not
> balanced
>
>
> *NOR*
Ashwini Mallad
for a nor gate low to high transition happens when both the pmos are
ON. now we have increased the width of pmos so area has increased and
resistance decreased.
We found that to get equal delays the sizes should be equal so that RC
will be equal and hence the delay will be equal.
now R of pmos is decreasing so load cap will charge quicker compared
to prevoius case.
hence the variation.
We can also see the tphl is increasing. this is because the pmos
device's area has increased and hence the drain capacitance has
increased increasing the time to discharge.
Hope this was helpful and Please update me if you find out more about this.
Thanking you,
Ashwini Mallad