Linux Kernel Patch v2.4, patch-2.4.10 (180/197)
Thomas Kobienia
#!/bin/sh -x
# this is part 180 of a 197 - part archive
# do not concatenate these parts, unpack them in order with /bin/sh
# file patch-2.4.10 continued
if test ! -r _shar_seq_.tmp; then
echo 'Please unpack part 1 first!'
exit 1
fi
(read Scheck
if test "$Scheck" != 180; then
echo "Please unpack part $Scheck next!"
exit 1
else
exit 0
fi
) < _shar_seq_.tmp || exit 1
if test ! -f _shar_wnt_.tmp; then
echo 'x - still skipping patch-2.4.10'
else
echo 'x - continuing with patch-2.4.10'
sed 's/^X//' << 'SHAR_EOF' >> 'patch-2.4.10' &&
X * License. See the file "COPYING" in the main directory of this archive
X * for more details.
@@ -114,7 +113,7 @@
X }
X
X /*
- * isa_slot_offset is the address where E(ISA) busaddress 0 is is mapped
+ * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped
X * for the processor. This implies the assumption that there is only
X * one of these busses.
X */
diff -u --recursive --new-file v2.4.9/linux/include/asm-mips64/ioctl.h linux/include/asm-mips64/ioctl.h
--- v2.4.9/linux/include/asm-mips64/ioctl.h Wed Jul 25 17:10:25 2001
+++ linux/include/asm-mips64/ioctl.h Sun Sep 9 10:43:02 2001
@@ -38,6 +38,11 @@
X #define _IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS)
X
X /*
+ * We to additionally limit parameters to a maximum 255 bytes.
+ */
+#define _IOC_SLMASK 0xff
+
+/*
X * Direction bits _IOC_NONE could be 0, but OSF/1 gives it a bit.
X * And this turns out useful to catch old ioctl numbers in header
X * files for us.
diff -u --recursive --new-file v2.4.9/linux/include/asm-mips64/ioctls.h linux/include/asm-mips64/ioctls.h
--- v2.4.9/linux/include/asm-mips64/ioctls.h Sat May 13 08:31:25 2000
+++ linux/include/asm-mips64/ioctls.h Sun Sep 9 10:43:02 2001
@@ -1,20 +1,16 @@
-/* $Id$
- *
+/*
X * This file is subject to the terms and conditions of the GNU General Public
X * License. See the file "COPYING" in the main directory of this archive
X * for more details.
X *
- * Copyright (C) 1995, 1996, 1999 by Ralf Baechle
+ * Copyright (C) 1995, 1996, 2001 Ralf Baechle
+ * Copyright (C) 2001 MIPS Technologies, Inc.
X */
-#ifndef _ASM_IOCTLS_H
-#define _ASM_IOCTLS_H
+#ifndef __ASM_IOCTLS_H
+#define __ASM_IOCTLS_H
X
X #include <asm/ioctl.h>
X
-#if defined(__USE_MISC) || defined (__KERNEL__)
-#define tIOC ('t' << 8)
-#endif
-
X #define TCGETA 0x5401
X #define TCSETA 0x5402
X #define TCSETAW 0x5403
@@ -38,31 +34,28 @@
X #define TIOCMBIC 0x741c /* bic modem bits */
X #define TIOCMSET 0x741a /* set all modem bits */
X #define TIOCPKT 0x5470 /* pty: set/clear packet mode */
-#define TIOCPKT_DATA 0x00 /* data packet */
-#define TIOCPKT_FLUSHREAD 0x01 /* flush packet */
-#define TIOCPKT_FLUSHWRITE 0x02 /* flush packet */
-#define TIOCPKT_STOP 0x04 /* stop output */
-#define TIOCPKT_START 0x08 /* start output */
-#define TIOCPKT_NOSTOP 0x10 /* no more ^S, ^Q */
-#define TIOCPKT_DOSTOP 0x20 /* now do ^S ^Q */
-#if 0
-#define TIOCPKT_IOCTL 0x40 /* state change of pty driver */
-#endif
+#define TIOCPKT_DATA 0x00 /* data packet */
+#define TIOCPKT_FLUSHREAD 0x01 /* flush packet */
+#define TIOCPKT_FLUSHWRITE 0x02 /* flush packet */
+#define TIOCPKT_STOP 0x04 /* stop output */
+#define TIOCPKT_START 0x08 /* start output */
+#define TIOCPKT_NOSTOP 0x10 /* no more ^S, ^Q */
+#define TIOCPKT_DOSTOP 0x20 /* now do ^S ^Q */
+/* #define TIOCPKT_IOCTL 0x40 state change of pty driver */
X #define TIOCSWINSZ _IOW('t', 103, struct winsize) /* set window size */
X #define TIOCGWINSZ _IOR('t', 104, struct winsize) /* get window size */
X #define TIOCNOTTY 0x5471 /* void tty association */
-#define TIOCSETD (tIOC | 1)
-#define TIOCGETD (tIOC | 0)
+#define TIOCSETD 0x7401
+#define TIOCGETD 0x7400
X
X #define FIOCLEX 0x6601
X #define FIONCLEX 0x6602 /* these numbers need to be adjusted. */
X #define FIOASYNC 0x667d
X #define FIONBIO 0x667e
+#define FIOQSIZE 0x667f
X
-#if defined(__USE_MISC) || defined (__KERNEL__)
-#define TIOCGLTC (tIOC | 116) /* get special local chars */
-#define TIOCSLTC (tIOC | 117) /* set special local chars */
-#endif
+#define TIOCGLTC 0x7474 /* get special local chars */
+#define TIOCSLTC 0x7475 /* set special local chars */
X #define TIOCSPGRP _IOW('t', 118, int) /* set pgrp of tty */
X #define TIOCGPGRP _IOR('t', 119, int) /* get pgrp of tty */
X #define TIOCCONS _IOW('t', 120, int) /* become virtual console */
@@ -70,20 +63,16 @@
X #define FIONREAD 0x467f
X #define TIOCINQ FIONREAD
X
-#if defined(__USE_MISC) || defined (__KERNEL__)
-#define TIOCGETP (tIOC | 8)
-#define TIOCSETP (tIOC | 9)
-#define TIOCSETN (tIOC | 10) /* TIOCSETP wo flush */
-#endif
+#define TIOCGETP 0x7408
+#define TIOCSETP 0x7409
+#define TIOCSETN 0x740a /* TIOCSETP wo flush */
X
-#if 0
-#define TIOCSETA _IOW('t', 20, struct termios) /* set termios struct */
-#define TIOCSETAW _IOW('t', 21, struct termios) /* drain output, set */
-#define TIOCSETAF _IOW('t', 22, struct termios) /* drn out, fls in, set */
-#define TIOCGETD _IOR('t', 26, int) /* get line discipline */
-#define TIOCSETD _IOW('t', 27, int) /* set line discipline */
+/* #define TIOCSETA _IOW('t', 20, struct termios) set termios struct */
+/* #define TIOCSETAW _IOW('t', 21, struct termios) drain output, set */
+/* #define TIOCSETAF _IOW('t', 22, struct termios) drn out, fls in, set */
+/* #define TIOCGETD _IOR('t', 26, int) get line discipline */
+/* #define TIOCSETD _IOW('t', 27, int) set line discipline */
X /* 127-124 compat */
-#endif
X
X /* I hope the range from 0x5480 on is free ... */
X #define TIOCSCTTY 0x5480 /* become controlling tty */
@@ -115,4 +104,4 @@
X #define TIOCGHAYESESP 0x5493 /* Get Hayes ESP configuration */
X #define TIOCSHAYESESP 0x5494 /* Set Hayes ESP configuration */
X
-#endif /* _ASM_IOCTLS_H */
+#endif /* __ASM_IOCTLS_H */
diff -u --recursive --new-file v2.4.9/linux/include/asm-mips64/keyboard.h linux/include/asm-mips64/keyboard.h
--- v2.4.9/linux/include/asm-mips64/keyboard.h Fri Apr 13 20:26:07 2001
+++ linux/include/asm-mips64/keyboard.h Sun Sep 9 10:43:02 2001
@@ -1,10 +1,10 @@
-/* $Id: keyboard.h,v 1.1 1999/08/19 22:56:34 ralf Exp $
- *
+/*
X * This file is subject to the terms and conditions of the GNU General Public
X * License. See the file "COPYING" in the main directory of this archive
X * for more details.
X *
- * Copyright (C) 1994 - 1999 Ralf Baechle
+ * Copyright (C) 1994 - 1999, 2001 Ralf Baechle
+ * Copyright (C) 2001 MIPS Technologies, Inc.
X */
X #ifndef _ASM_KEYBOARD_H
X #define _ASM_KEYBOARD_H
@@ -13,6 +13,7 @@
X
X #include <linux/delay.h>
X #include <linux/ioport.h>
+#include <linux/kd.h>
X #include <asm/bootinfo.h>
X
X #define DISABLE_KBD_DURING_INTERRUPTS 0
@@ -23,6 +24,7 @@
X char raw_mode);
X extern char pckbd_unexpected_up(unsigned char keycode);
X extern void pckbd_leds(unsigned char leds);
+extern int pckbd_rate(struct kbd_repeat *rep);
X extern void pckbd_init_hw(void);
X extern unsigned char pckbd_sysrq_xlate[128];
X
@@ -31,6 +33,7 @@
X #define kbd_translate pckbd_translate
X #define kbd_unexpected_up pckbd_unexpected_up
X #define kbd_leds pckbd_leds
+#define kbd_rate pckbd_rate
X #define kbd_init_hw pckbd_init_hw
X #define kbd_sysrq_xlate pckbd_sysrq_xlate
X
diff -u --recursive --new-file v2.4.9/linux/include/asm-mips64/linux_logo.h linux/include/asm-mips64/linux_logo.h
--- v2.4.9/linux/include/asm-mips64/linux_logo.h Tue Jul 3 17:08:21 2001
+++ linux/include/asm-mips64/linux_logo.h Sun Sep 9 10:43:02 2001
@@ -1,5 +1,4 @@
-/* $Id$
- *
+/*
X * include/asm-mips/linux_logo.h: This is a linux logo
X * to be displayed on boot.
X *
diff -u --recursive --new-file v2.4.9/linux/include/asm-mips64/mc146818rtc.h linux/include/asm-mips64/mc146818rtc.h
--- v2.4.9/linux/include/asm-mips64/mc146818rtc.h Thu Jul 27 18:36:54 2000
+++ linux/include/asm-mips64/mc146818rtc.h Sun Sep 9 10:43:02 2001
@@ -1,5 +1,4 @@
-/* $Id$
- *
+/*
X * This file is subject to the terms and conditions of the GNU General Public
X * License. See the file "COPYING" in the main directory of this archive
X * for more details.
diff -u --recursive --new-file v2.4.9/linux/include/asm-mips64/mips-boards/atlas.h linux/include/asm-mips64/mips-boards/atlas.h
--- v2.4.9/linux/include/asm-mips64/mips-boards/atlas.h Wed Dec 31 16:00:00 1969
+++ linux/include/asm-mips64/mips-boards/atlas.h Sun Sep 9 10:43:02 2001
@@ -0,0 +1,62 @@
+/*
+ * Carsten Langgaard, cars...@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
+ *
+ * ########################################################################
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ * Defines of the Atlas board specific address-MAP, registers, etc.
+ *
+ */
+#ifndef _MIPS_ATLAS_H
+#define _MIPS_ATLAS_H
+
+#include <asm/addrspace.h>
+
+/*
+ * Atlas RTC-device indirect register access.
+ */
+#define ATLAS_RTC_ADR_REG (KSEG1ADDR(0x1f000800))
+#define ATLAS_RTC_DAT_REG (KSEG1ADDR(0x1f000808))
+
+
+/*
+ * Atlas interrupt controller register base.
+ */
+#define ATLAS_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000))
+
+/*
+ * Atlas UART register base.
+ */
+#define ATLAS_UART_REGS_BASE (0x1f000900)
+#define ATLAS_BASE_BAUD ( 3686400 / 16 )
+
+/*
+ * Atlas PSU standby register.
+ */
+#define ATLAS_PSUSTBY_REG (KSEG1ADDR(0x1f000600))
+#define ATLAS_GOSTBY 0x4d
+
+/*
+ * We make a universal assumption about the way the bootloader (YAMON)
+ * have located the Philips SAA9730 chip.
+ * This is not ideal, but is needed for setting up remote debugging as
+ * soon as possible.
+ */
+#define ATLAS_SAA9730_REG (KSEG1ADDR(0x08800000))
+
+#endif /* !(_MIPS_ATLAS_H) */
diff -u --recursive --new-file v2.4.9/linux/include/asm-mips64/mips-boards/atlasint.h linux/include/asm-mips64/mips-boards/atlasint.h
--- v2.4.9/linux/include/asm-mips64/mips-boards/atlasint.h Wed Dec 31 16:00:00 1969
+++ linux/include/asm-mips64/mips-boards/atlasint.h Sun Sep 9 10:43:02 2001
@@ -0,0 +1,51 @@
+/*
+ * Carsten Langgaard, cars...@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
+ *
+ * ########################################################################
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ * Defines for the Atlas interrupt controller.
+ *
+ */
+#ifndef _MIPS_ATLASINT_H
+#define _MIPS_ATLASINT_H
+
+/* Number of IRQ supported on hw interrupt 0. */
+#define ATLASINT_UART 0
+#define ATLASINT_END 32
+
+/*
+ * Atlas registers are memory mapped on 64-bit aligned boundaries and
+ * only word access are allowed.
+ */
+struct atlas_ictrl_regs {
+ volatile unsigned long intraw;
+ long dummy1;
+ volatile unsigned long intseten;
+ long dummy2;
+ volatile unsigned long intrsten;
+ long dummy3;
+ volatile unsigned long intenable;
+ long dummy4;
+ volatile unsigned long intstatus;
+ long dummy5;
+};
+
+extern void atlasint_init(void);
+
+#endif /* !(_MIPS_ATLASINT_H) */
diff -u --recursive --new-file v2.4.9/linux/include/asm-mips64/mips-boards/generic.h linux/include/asm-mips64/mips-boards/generic.h
--- v2.4.9/linux/include/asm-mips64/mips-boards/generic.h Wed Dec 31 16:00:00 1969
+++ linux/include/asm-mips64/mips-boards/generic.h Sun Sep 9 10:43:01 2001
@@ -0,0 +1,70 @@
+/*
+ * Carsten Langgaard, cars...@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
+ *
+ * ########################################################################
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ * Defines of the MIPS boards specific address-MAP, registers, etc.
+ *
+ */
+#ifndef _MIPS_GENERIC_H
+#define _MIPS_GENERIC_H
+
+#include <asm/addrspace.h>
+#include <asm/byteorder.h>
+
+/*
+ * Display register base.
+ */
+#define ASCII_DISPLAY_WORD_BASE (KSEG1ADDR(0x1f000410))
+#define ASCII_DISPLAY_POS_BASE (KSEG1ADDR(0x1f000418))
+
+
+/*
+ * Yamon Prom print address.
+ */
+#define YAMON_PROM_PRINT_ADDR (KSEG1ADDR(0x1fc00504))
+
+
+/*
+ * Reset register.
+ */
+#define SOFTRES_REG (KSEG1ADDR(0x1f000500))
+#define GORESET 0x42
+
+
+/*
+ * Galileo GT64120 system controller register base.
+ */
+#define MIPS_GT_BASE (KSEG1ADDR(0x1be00000))
+
+/*
+ * Because of the way the internal register works on the Galileo chip,
+ * we need to swap the bytes when running bigendian.
+ */
+#define GT_WRITE(ofs, data) \
+ *(volatile u32 *)(MIPS_GT_BASE+ofs) = cpu_to_le32(data)
+#define GT_READ(ofs, data) \
+ data = le32_to_cpu(*(volatile u32 *)(MIPS_GT_BASE+ofs))
+
+#define GT_PCI_WRITE(ofs, data) \
+ *(volatile u32 *)(MIPS_GT_BASE+ofs) = data
+#define GT_PCI_READ(ofs, data) \
+ data = *(volatile u32 *)(MIPS_GT_BASE+ofs)
+
+#endif /* !(_MIPS_GENERIC_H) */
diff -u --recursive --new-file v2.4.9/linux/include/asm-mips64/mips-boards/gt64120.h linux/include/asm-mips64/mips-boards/gt64120.h
--- v2.4.9/linux/include/asm-mips64/mips-boards/gt64120.h Wed Dec 31 16:00:00 1969
+++ linux/include/asm-mips64/mips-boards/gt64120.h Sun Sep 9 10:43:01 2001
@@ -0,0 +1,337 @@
+/*
+ * Carsten Langgaard, cars...@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
+ *
+ * ########################################################################
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ * Register definitions for Galileo 64120 system controller.
+ *
+ */
+#ifndef GT64120_H
+#define GT64120_H
+
+#define MSK(n) ((1 << (n)) - 1)
+
+/************************************************************************
+ * Register offset addresses
+ ************************************************************************/
+
+#define GT_CPU_OFS 0x000
+
+#define GT_CPU_OFS 0x000
+#define GT_SCS10LD_OFS 0x008
+#define GT_SCS10HD_OFS 0x010
+#define GT_SCS32LD_OFS 0x018
+#define GT_SCS32HD_OFS 0x020
+#define GT_CS20LD_OFS 0x028
+#define GT_CS20HD_OFS 0x030
+#define GT_CS3BOOTLD_OFS 0x038
+#define GT_CS3BOOTHD_OFS 0x040
+#define GT_PCI0IOLD_OFS 0x048
+#define GT_PCI0IOHD_OFS 0x050
+#define GT_PCI0M0LD_OFS 0x058
+#define GT_PCI0M0HD_OFS 0x060
+#define GT_ISD_OFS 0x068
+#define GT_PCI0M1LD_OFS 0x080
+#define GT_PCI0M1HD_OFS 0x088
+#define GT_PCI1IOLD_OFS 0x090
+#define GT_PCI1IOHD_OFS 0x098
+#define GT_PCI1M0LD_OFS 0x0a0
+#define GT_PCI1M0HD_OFS 0x0a8
+#define GT_PCI1M1LD_OFS 0x0b0
+#define GT_PCI1M1HD_OFS 0x0b8
+
+#define GT_SCS0LD_OFS 0x400
+#define GT_SCS0HD_OFS 0x404
+#define GT_SCS1LD_OFS 0x408
+#define GT_SCS1HD_OFS 0x40c
+#define GT_SCS2LD_OFS 0x410
+#define GT_SCS2HD_OFS 0x414
+#define GT_SCS3LD_OFS 0x418
+#define GT_SCS3HD_OFS 0x41c
+#define GT_CS0LD_OFS 0x420
+#define GT_CS0HD_OFS 0x424
+#define GT_CS1LD_OFS 0x428
+#define GT_CS1HD_OFS 0x42c
+#define GT_CS2LD_OFS 0x430
+#define GT_CS2HD_OFS 0x434
+#define GT_CS3LD_OFS 0x438
+#define GT_CS3HD_OFS 0x43c
+#define GT_BOOTLD_OFS 0x440
+#define GT_BOOTHD_OFS 0x444
+
+#define GT_SDRAM_B0_OFS 0x44c
+#define GT_SDRAM_CFG_OFS 0x448
+#define GT_SDRAM_B2_OFS 0x454
+#define GT_SDRAM_OPMODE_OFS 0x474
+#define GT_SDRAM_BM_OFS 0x478
+#define GT_SDRAM_ADDRDECODE_OFS 0x47c
+
+#define GT_PCI0_CMD_OFS 0xc00
+#define GT_PCI0_TOR_OFS 0xc04
+#define GT_PCI0_BS_SCS10_OFS 0xc08
+#define GT_PCI0_BS_SCS32_OFS 0xc0c
+#define GT_INTRCAUSE_OFS 0xc18
+#define GT_PCI0_IACK_OFS 0xc34
+#define GT_PCI0_BARE_OFS 0xc3c
+#define GT_PCI0_CFGADDR_OFS 0xcf8
+#define GT_PCI0_CFGDATA_OFS 0xcfc
+
+
+
+
+/************************************************************************
+ * Register encodings
+ ************************************************************************/
+
+#define GT_CPU_ENDIAN_SHF 12
+#define GT_CPU_ENDIAN_MSK (MSK(1) << GT_CPU_ENDIAN_SHF)
+#define GT_CPU_ENDIAN_BIT GT_CPU_ENDIAN_MSK
+#define GT_CPU_WR_SHF 16
+#define GT_CPU_WR_MSK (MSK(1) << GT_CPU_WR_SHF)
+#define GT_CPU_WR_BIT GT_CPU_WR_MSK
+#define GT_CPU_WR_DXDXDXDX 0
+#define GT_CPU_WR_DDDD 1
+
+
+#define GT_CFGADDR_CFGEN_SHF 31
+#define GT_CFGADDR_CFGEN_MSK (MSK(1) << GT_CFGADDR_CFGEN_SHF)
+#define GT_CFGADDR_CFGEN_BIT GT_CFGADDR_CFGEN_MSK
+
+#define GT_CFGADDR_BUSNUM_SHF 16
+#define GT_CFGADDR_BUSNUM_MSK (MSK(8) << GT_CFGADDR_BUSNUM_SHF)
+
+#define GT_CFGADDR_DEVNUM_SHF 11
+#define GT_CFGADDR_DEVNUM_MSK (MSK(5) << GT_CFGADDR_DEVNUM_SHF)
+
+#define GT_CFGADDR_FUNCNUM_SHF 8
+#define GT_CFGADDR_FUNCNUM_MSK (MSK(3) << GT_CFGADDR_FUNCNUM_SHF)
+
+#define GT_CFGADDR_REGNUM_SHF 2
+#define GT_CFGADDR_REGNUM_MSK (MSK(6) << GT_CFGADDR_REGNUM_SHF)
+
+
+#define GT_SDRAM_BM_ORDER_SHF 2
+#define GT_SDRAM_BM_ORDER_MSK (MSK(1) << GT_SDRAM_BM_ORDER_SHF)
+#define GT_SDRAM_BM_ORDER_BIT GT_SDRAM_BM_ORDER_MSK
+#define GT_SDRAM_BM_ORDER_SUB 1
+#define GT_SDRAM_BM_ORDER_LIN 0
+
+#define GT_SDRAM_BM_RSVD_ALL1 0xFFB
+
+
+#define GT_SDRAM_ADDRDECODE_ADDR_SHF 0
+#define GT_SDRAM_ADDRDECODE_ADDR_MSK (MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF)
+#define GT_SDRAM_ADDRDECODE_ADDR_0 0
+#define GT_SDRAM_ADDRDECODE_ADDR_1 1
+#define GT_SDRAM_ADDRDECODE_ADDR_2 2
+#define GT_SDRAM_ADDRDECODE_ADDR_3 3
+#define GT_SDRAM_ADDRDECODE_ADDR_4 4
+#define GT_SDRAM_ADDRDECODE_ADDR_5 5
+#define GT_SDRAM_ADDRDECODE_ADDR_6 6
+#define GT_SDRAM_ADDRDECODE_ADDR_7 7
+
+
+#define GT_SDRAM_B0_CASLAT_SHF 0
+#define GT_SDRAM_B0_CASLAT_MSK (MSK(2) << GT_SDRAM_B0__SHF)
+#define GT_SDRAM_B0_CASLAT_2 1
+#define GT_SDRAM_B0_CASLAT_3 2
+
+#define GT_SDRAM_B0_FTDIS_SHF 2
+#define GT_SDRAM_B0_FTDIS_MSK (MSK(1) << GT_SDRAM_B0_FTDIS_SHF)
+#define GT_SDRAM_B0_FTDIS_BIT GT_SDRAM_B0_FTDIS_MSK
+
+#define GT_SDRAM_B0_SRASPRCHG_SHF 3
+#define GT_SDRAM_B0_SRASPRCHG_MSK (MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF)
+#define GT_SDRAM_B0_SRASPRCHG_BIT GT_SDRAM_B0_SRASPRCHG_MSK
+#define GT_SDRAM_B0_SRASPRCHG_2 0
+#define GT_SDRAM_B0_SRASPRCHG_3 1
+
+#define GT_SDRAM_B0_B0COMPAB_SHF 4
+#define GT_SDRAM_B0_B0COMPAB_MSK (MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF)
+#define GT_SDRAM_B0_B0COMPAB_BIT GT_SDRAM_B0_B0COMPAB_MSK
+
+#define GT_SDRAM_B0_64BITINT_SHF 5
+#define GT_SDRAM_B0_64BITINT_MSK (MSK(1) << GT_SDRAM_B0_64BITINT_SHF)
+#define GT_SDRAM_B0_64BITINT_BIT GT_SDRAM_B0_64BITINT_MSK
+#define GT_SDRAM_B0_64BITINT_2 0
+#define GT_SDRAM_B0_64BITINT_4 1
+
+#define GT_SDRAM_B0_BW_SHF 6
+#define GT_SDRAM_B0_BW_MSK (MSK(1) << GT_SDRAM_B0_BW_SHF)
+#define GT_SDRAM_B0_BW_BIT GT_SDRAM_B0_BW_MSK
+#define GT_SDRAM_B0_BW_32 0
+#define GT_SDRAM_B0_BW_64 1
+
+#define GT_SDRAM_B0_BLODD_SHF 7
+#define GT_SDRAM_B0_BLODD_MSK (MSK(1) << GT_SDRAM_B0_BLODD_SHF)
+#define GT_SDRAM_B0_BLODD_BIT GT_SDRAM_B0_BLODD_MSK
+
+#define GT_SDRAM_B0_PAR_SHF 8
+#define GT_SDRAM_B0_PAR_MSK (MSK(1) << GT_SDRAM_B0_PAR_SHF)
+#define GT_SDRAM_B0_PAR_BIT GT_SDRAM_B0_PAR_MSK
+
+#define GT_SDRAM_B0_BYPASS_SHF 9
+#define GT_SDRAM_B0_BYPASS_MSK (MSK(1) << GT_SDRAM_B0_BYPASS_SHF)
+#define GT_SDRAM_B0_BYPASS_BIT GT_SDRAM_B0_BYPASS_MSK
+
+#define GT_SDRAM_B0_SRAS2SCAS_SHF 10
+#define GT_SDRAM_B0_SRAS2SCAS_MSK (MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF)
+#define GT_SDRAM_B0_SRAS2SCAS_BIT GT_SDRAM_B0_SRAS2SCAS_MSK
+#define GT_SDRAM_B0_SRAS2SCAS_2 0
+#define GT_SDRAM_B0_SRAS2SCAS_3 1
+
+#define GT_SDRAM_B0_SIZE_SHF 11
+#define GT_SDRAM_B0_SIZE_MSK (MSK(1) << GT_SDRAM_B0_SIZE_SHF)
+#define GT_SDRAM_B0_SIZE_BIT GT_SDRAM_B0_SIZE_MSK
+#define GT_SDRAM_B0_SIZE_16M 0
+#define GT_SDRAM_B0_SIZE_64M 1
+
+#define GT_SDRAM_B0_EXTPAR_SHF 12
+#define GT_SDRAM_B0_EXTPAR_MSK (MSK(1) << GT_SDRAM_B0_EXTPAR_SHF)
+#define GT_SDRAM_B0_EXTPAR_BIT GT_SDRAM_B0_EXTPAR_MSK
+
+#define GT_SDRAM_B0_BLEN_SHF 13
+#define GT_SDRAM_B0_BLEN_MSK (MSK(1) << GT_SDRAM_B0_BLEN_SHF)
+#define GT_SDRAM_B0_BLEN_BIT GT_SDRAM_B0_BLEN_MSK
+#define GT_SDRAM_B0_BLEN_8 0
+#define GT_SDRAM_B0_BLEN_4 1
+
+
+#define GT_SDRAM_CFG_REFINT_SHF 0
+#define GT_SDRAM_CFG_REFINT_MSK (MSK(14) << GT_SDRAM_CFG_REFINT_SHF)
+
+#define GT_SDRAM_CFG_NINTERLEAVE_SHF 14
+#define GT_SDRAM_CFG_NINTERLEAVE_MSK (MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF)
+#define GT_SDRAM_CFG_NINTERLEAVE_BIT GT_SDRAM_CFG_NINTERLEAVE_MSK
+
+#define GT_SDRAM_CFG_RMW_SHF 15
+#define GT_SDRAM_CFG_RMW_MSK (MSK(1) << GT_SDRAM_CFG_RMW_SHF)
+#define GT_SDRAM_CFG_RMW_BIT GT_SDRAM_CFG_RMW_MSK
+
+#define GT_SDRAM_CFG_NONSTAGREF_SHF 16
+#define GT_SDRAM_CFG_NONSTAGREF_MSK (MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF)
+#define GT_SDRAM_CFG_NONSTAGREF_BIT GT_SDRAM_CFG_NONSTAGREF_MSK
+
+#define GT_SDRAM_CFG_DUPCNTL_SHF 19
+#define GT_SDRAM_CFG_DUPCNTL_MSK (MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF)
+#define GT_SDRAM_CFG_DUPCNTL_BIT GT_SDRAM_CFG_DUPCNTL_MSK
+
+#define GT_SDRAM_CFG_DUPBA_SHF 20
+#define GT_SDRAM_CFG_DUPBA_MSK (MSK(1) << GT_SDRAM_CFG_DUPBA_SHF)
+#define GT_SDRAM_CFG_DUPBA_BIT GT_SDRAM_CFG_DUPBA_MSK
+
+#define GT_SDRAM_CFG_DUPEOT0_SHF 21
+#define GT_SDRAM_CFG_DUPEOT0_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF)
+#define GT_SDRAM_CFG_DUPEOT0_BIT GT_SDRAM_CFG_DUPEOT0_MSK
+
+#define GT_SDRAM_CFG_DUPEOT1_SHF 22
+#define GT_SDRAM_CFG_DUPEOT1_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF)
+#define GT_SDRAM_CFG_DUPEOT1_BIT GT_SDRAM_CFG_DUPEOT1_MSK
+
+#define GT_SDRAM_OPMODE_OP_SHF 0
+#define GT_SDRAM_OPMODE_OP_MSK (MSK(3) << GT_SDRAM_OPMODE_OP_SHF)
+#define GT_SDRAM_OPMODE_OP_NORMAL 0
+#define GT_SDRAM_OPMODE_OP_NOP 1
+#define GT_SDRAM_OPMODE_OP_PRCHG 2
+#define GT_SDRAM_OPMODE_OP_MODE 3
+#define GT_SDRAM_OPMODE_OP_CBR 4
+
+
+#define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0
+#define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF)
+#define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT GT_PCI0_BARE_SWSCS3BOOTDIS_MSK
+
+#define GT_PCI0_BARE_SWSCS32DIS_SHF 1
+#define GT_PCI0_BARE_SWSCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF)
+#define GT_PCI0_BARE_SWSCS32DIS_BIT GT_PCI0_BARE_SWSCS32DIS_MSK
+
+#define GT_PCI0_BARE_SWSCS10DIS_SHF 2
+#define GT_PCI0_BARE_SWSCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF)
+#define GT_PCI0_BARE_SWSCS10DIS_BIT GT_PCI0_BARE_SWSCS10DIS_MSK
+
+#define GT_PCI0_BARE_INTIODIS_SHF 3
+#define GT_PCI0_BARE_INTIODIS_MSK (MSK(1) << GT_PCI0_BARE_INTIODIS_SHF)
+#define GT_PCI0_BARE_INTIODIS_BIT GT_PCI0_BARE_INTIODIS_MSK
+
+#define GT_PCI0_BARE_INTMEMDIS_SHF 4
+#define GT_PCI0_BARE_INTMEMDIS_MSK (MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF)
+#define GT_PCI0_BARE_INTMEMDIS_BIT GT_PCI0_BARE_INTMEMDIS_MSK
+
+#define GT_PCI0_BARE_CS3BOOTDIS_SHF 5
+#define GT_PCI0_BARE_CS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF)
+#define GT_PCI0_BARE_CS3BOOTDIS_BIT GT_PCI0_BARE_CS3BOOTDIS_MSK
+
+#define GT_PCI0_BARE_CS20DIS_SHF 6
+#define GT_PCI0_BARE_CS20DIS_MSK (MSK(1) << GT_PCI0_BARE_CS20DIS_SHF)
+#define GT_PCI0_BARE_CS20DIS_BIT GT_PCI0_BARE_CS20DIS_MSK
+
+#define GT_PCI0_BARE_SCS32DIS_SHF 7
+#define GT_PCI0_BARE_SCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF)
+#define GT_PCI0_BARE_SCS32DIS_BIT GT_PCI0_BARE_SCS32DIS_MSK
+
+#define GT_PCI0_BARE_SCS10DIS_SHF 8
+#define GT_PCI0_BARE_SCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF)
+#define GT_PCI0_BARE_SCS10DIS_BIT GT_PCI0_BARE_SCS10DIS_MSK
+
+
+#define GT_INTRCAUSE_MASABORT0_SHF 18
+#define GT_INTRCAUSE_MASABORT0_MSK (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF)
+#define GT_INTRCAUSE_MASABORT0_BIT GT_INTRCAUSE_MASABORT0_MSK
+
+#define GT_INTRCAUSE_TARABORT0_SHF 19
+#define GT_INTRCAUSE_TARABORT0_MSK (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF)
+#define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK
+
+
+#define GT_PCI0_CFGADDR_REGNUM_SHF 2
+#define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF)
+#define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8
+#define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF)
+#define GT_PCI0_CFGADDR_DEVNUM_SHF 11
+#define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF)
+#define GT_PCI0_CFGADDR_BUSNUM_SHF 16
+#define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF)
+#define GT_PCI0_CFGADDR_CONFIGEN_SHF 31
+#define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF)
+#define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK
+
+#define GT_PCI0_CMD_MBYTESWAP_SHF 0
+#define GT_PCI0_CMD_MBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF)
+#define GT_PCI0_CMD_MBYTESWAP_BIT GT_PCI0_CMD_MBYTESWAP_MSK
+#define GT_PCI0_CMD_MWORDSWAP_SHF 10
+#define GT_PCI0_CMD_MWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_MWORDSWAP_SHF)
+#define GT_PCI0_CMD_MWORDSWAP_BIT GT_PCI0_CMD_MWORDSWAP_MSK
+#define GT_PCI0_CMD_SBYTESWAP_SHF 16
+#define GT_PCI0_CMD_SBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_SBYTESWAP_SHF)
+#define GT_PCI0_CMD_SBYTESWAP_BIT GT_PCI0_CMD_SBYTESWAP_MSK
+#define GT_PCI0_CMD_SWORDSWAP_SHF 11
+#define GT_PCI0_CMD_SWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF)
+#define GT_PCI0_CMD_SWORDSWAP_BIT GT_PCI0_CMD_SWORDSWAP_MSK
+
+
+/************************************************************************
+ * Misc
+ ************************************************************************/
+
+#define GT_DEF_BASE 0x14000000
+#define GT_DEF_PCI0_MEM0_BASE 0x12000000
+#define GT_MAX_BANKSIZE (256 * 1024 * 1024) /* Max 256MB bank */
+#define GT_LATTIM_MIN 6 /* Minimum lat */
+
+#endif /* #ifndef GT64120_H */
diff -u --recursive --new-file v2.4.9/linux/include/asm-mips64/mips-boards/io.h linux/include/asm-mips64/mips-boards/io.h
--- v2.4.9/linux/include/asm-mips64/mips-boards/io.h Wed Dec 31 16:00:00 1969
+++ linux/include/asm-mips64/mips-boards/io.h Sun Sep 9 10:43:02 2001
@@ -0,0 +1,34 @@
+/*
+ * Carsten Langgaard, cars...@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
+ *
+ * ########################################################################
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ * Defines of the MIPS boards specific IO address-MAP.
+ *
+ */
+#ifndef _ASM_MIPS_BOARDS_IO_H
+#define _ASM_MIPS_BOARDS_IO_H
+
+#include <asm/addrspace.h>
+
+#define IO_SPACE_BASE K1BASE
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+#endif /* _ASM_MIPS_BOARDS_IO_H */
diff -u --recursive --new-file v2.4.9/linux/include/asm-mips64/mips-boards/malta.h linux/include/asm-mips64/mips-boards/malta.h
--- v2.4.9/linux/include/asm-mips64/mips-boards/malta.h Wed Dec 31 16:00:00 1969
+++ linux/include/asm-mips64/mips-boards/malta.h Sun Sep 9 10:43:02 2001
@@ -0,0 +1,59 @@
+/*
+ * Carsten Langgaard, cars...@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
+ *
+ * ########################################################################
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ * Defines of the Malta board specific address-MAP, registers, etc.
+ *
+ */
+#ifndef _MIPS_MALTA_H
+#define _MIPS_MALTA_H
+
+#include <asm/addrspace.h>
+#include <asm/io.h>
+
+/*
+ * Malta I/O ports base address.
+*/
+#define MALTA_PORT_BASE (KSEG1ADDR(0x18000000))
+
+/*
+ * Malta RTC-device indirect register access.
+ */
+#define MALTA_RTC_ADR_REG 0x70
+#define MALTA_RTC_DAT_REG 0x71
+
+/*
+ * Malta SMSC FDC37M817 Super I/O Controller register.
+ */
+#define SMSC_CONFIG_REG 0x3f0
+#define SMSC_DATA_REG 0x3f1
+
+#define SMSC_CONFIG_DEVNUM 0x7
+#define SMSC_CONFIG_ACTIVATE 0x30
+#define SMSC_CONFIG_ENTER 0x55
+#define SMSC_CONFIG_EXIT 0xaa
+
+#define SMSC_CONFIG_DEVNUM_FLOPPY 0
+
+#define SMSC_CONFIG_ACTIVATE_ENABLE 1
+
+#define SMSC_WRITE(x,a) outb(x,a)
+
+#endif /* !(_MIPS_MALTA_H) */
diff -u --recursive --new-file v2.4.9/linux/include/asm-mips64/mips-boards/maltaint.h linux/include/asm-mips64/mips-boards/maltaint.h
--- v2.4.9/linux/include/asm-mips64/mips-boards/maltaint.h Wed Dec 31 16:00:00 1969
+++ linux/include/asm-mips64/mips-boards/maltaint.h Sun Sep 9 10:43:02 2001
@@ -0,0 +1,33 @@
+/*
+ * Carsten Langgaard, cars...@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
+ *
+ * ########################################################################
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ * Defines for the Malta interrupt controller.
+ *
+ */
+#ifndef _MIPS_MALTAINT_H
+#define _MIPS_MALTAINT_H
+
+/* Number of IRQ supported on hw interrupt 0. */
+#define MALTAINT_END 16
+
+extern void maltaint_init(void);
+
+#endif /* !(_MIPS_MALTAINT_H) */
diff -u --recursive --new-file v2.4.9/linux/include/asm-mips64/mips-boards/piix4.h linux/include/asm-mips64/mips-boards/piix4.h
--- v2.4.9/linux/include/asm-mips64/mips-boards/piix4.h Wed Dec 31 16:00:00 1969
+++ linux/include/asm-mips64/mips-boards/piix4.h Sun Sep 9 10:43:02 2001
@@ -0,0 +1,86 @@
+/*
+ * Carsten Langgaard, cars...@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
+ *
+ * ########################################################################
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ * Register definitions for Intel PIIX4 South Bridge Device.
+ *
+ */
+
+#ifndef PIIX4_H
+#define PIIX4_H
+
+/************************************************************************
+ * IO register offsets
+ ************************************************************************/
+#define PIIX4_ICTLR1_ICW1 0x20
+#define PIIX4_ICTLR1_ICW2 0x21
+#define PIIX4_ICTLR1_ICW3 0x21
+#define PIIX4_ICTLR1_ICW4 0x21
+#define PIIX4_ICTLR2_ICW1 0xa0
+#define PIIX4_ICTLR2_ICW2 0xa1
+#define PIIX4_ICTLR2_ICW3 0xa1
+#define PIIX4_ICTLR2_ICW4 0xa1
+#define PIIX4_ICTLR1_OCW1 0x21
+#define PIIX4_ICTLR1_OCW2 0x20
+#define PIIX4_ICTLR1_OCW3 0x20
+#define PIIX4_ICTLR1_OCW4 0x20
+#define PIIX4_ICTLR2_OCW1 0xa1
+#define PIIX4_ICTLR2_OCW2 0xa0
+#define PIIX4_ICTLR2_OCW3 0xa0
+#define PIIX4_ICTLR2_OCW4 0xa0
+
+
+/************************************************************************
+ * Register encodings.
+ ************************************************************************/
+#define PIIX4_OCW2_NSEOI (0x1 << 5)
+#define PIIX4_OCW2_SEOI (0x3 << 5)
+#define PIIX4_OCW2_RNSEOI (0x5 << 5)
+#define PIIX4_OCW2_RAEOIS (0x4 << 5)
+#define PIIX4_OCW2_RAEOIC (0x0 << 5)
+#define PIIX4_OCW2_RSEOI (0x7 << 5)
+#define PIIX4_OCW2_SP (0x6 << 5)
+#define PIIX4_OCW2_NOP (0x2 << 5)
+
+#define PIIX4_OCW2_SEL (0x0 << 3)
+
+#define PIIX4_OCW2_ILS_0 0
+#define PIIX4_OCW2_ILS_1 1
+#define PIIX4_OCW2_ILS_2 2
+#define PIIX4_OCW2_ILS_3 3
+#define PIIX4_OCW2_ILS_4 4
+#define PIIX4_OCW2_ILS_5 5
+#define PIIX4_OCW2_ILS_6 6
+#define PIIX4_OCW2_ILS_7 7
+#define PIIX4_OCW2_ILS_8 0
+#define PIIX4_OCW2_ILS_9 1
+#define PIIX4_OCW2_ILS_10 2
+#define PIIX4_OCW2_ILS_11 3
+#define PIIX4_OCW2_ILS_12 4
+#define PIIX4_OCW2_ILS_13 5
+#define PIIX4_OCW2_ILS_14 6
+#define PIIX4_OCW2_ILS_15 7
+
+#define PIIX4_OCW3_SEL (0x1 << 3)
+
+#define PIIX4_OCW3_IRR 0x2
+#define PIIX4_OCW3_ISR 0x3
+
+#endif /* !(PIIX4_H) */
diff -u --recursive --new-file v2.4.9/linux/include/asm-mips64/mips-boards/prom.h linux/include/asm-mips64/mips-boards/prom.h
--- v2.4.9/linux/include/asm-mips64/mips-boards/prom.h Wed Dec 31 16:00:00 1969
+++ linux/include/asm-mips64/mips-boards/prom.h Sun Sep 9 10:43:02 2001
@@ -0,0 +1,49 @@
+/*
+ * Carsten Langgaard, cars...@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
+ *
+ * ########################################################################
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ * MIPS boards bootprom interface for the Linux kernel.
+ *
+ */
+
+#ifndef _MIPS_PROM_H
+#define _MIPS_PROM_H
+
+extern char *prom_getcmdline(void);
+extern char *prom_getenv(char *name);
+extern void setup_prom_printf(int tty_no);
+extern void prom_printf(char *fmt, ...);
+extern void prom_init_cmdline(void);
+extern void prom_meminit(void);
+extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
+extern void prom_free_prom_memory (void);
+extern void mips_display_message(const char *str);
+extern void mips_display_word(unsigned int num);
+extern int get_ethernet_addr(char *ethernet_addr);
+
+/* Memory descriptor management. */
+#define PROM_MAX_PMEMBLOCKS 32
+struct prom_pmemblock {
+ unsigned int base; /* Phys addr. */
+ unsigned int size; /* In bytes. */
+ unsigned int type; /* free or prom memory */
+};
+
+#endif /* !(_MIPS_PROM_H) */
diff -u --recursive --new-file v2.4.9/linux/include/asm-mips64/mips-boards/saa9730_uart.h linux/include/asm-mips64/mips-boards/saa9730_uart.h
--- v2.4.9/linux/include/asm-mips64/mips-boards/saa9730_uart.h Wed Dec 31 16:00:00 1969
+++ linux/include/asm-mips64/mips-boards/saa9730_uart.h Sun Sep 9 10:43:02 2001
@@ -0,0 +1,69 @@
+/*
+ * Carsten Langgaard, cars...@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
+ *
+ * ########################################################################
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ * Register definitions for the UART part of the Philips SAA9730 chip.
+ *
+ */
+
+#ifndef SAA9730_UART_H
+#define SAA9730_UART_H
+
+/* The SAA9730 UART register map, as seen via the PCI bus */
+
+#define SAA9730_UART_REGS_ADDR 0x21800
+
+struct uart_saa9730_regmap {
+ volatile unsigned char Thr_Rbr;
+ volatile unsigned char Ier;
+ volatile unsigned char Iir_Fcr;
+ volatile unsigned char Lcr;
+ volatile unsigned char Mcr;
+ volatile unsigned char Lsr;
+ volatile unsigned char Msr;
+ volatile unsigned char Scr;
+ volatile unsigned char BaudDivLsb;
+ volatile unsigned char BaudDivMsb;
+ volatile unsigned char Junk0;
+ volatile unsigned char Junk1;
+ volatile unsigned int Config; /* 0x2180c */
+ volatile unsigned int TxStart; /* 0x21810 */
+ volatile unsigned int TxLength; /* 0x21814 */
+ volatile unsigned int TxCounter; /* 0x21818 */
+ volatile unsigned int RxStart; /* 0x2181c */
+ volatile unsigned int RxLength; /* 0x21820 */
+ volatile unsigned int RxCounter; /* 0x21824 */
+};
+typedef volatile struct uart_saa9730_regmap t_uart_saa9730_regmap;
+
+/*
+ * Only a subset of the UART control bits are defined here,
+ * enough to make the serial debug port work.
+ */
+
+#define SAA9730_LCR_DATA8 0x03
+
+#define SAA9730_MCR_DTR 0x01
+#define SAA9730_MCR_RTS 0x02
+
+#define SAA9730_LSR_DR 0x01
+#define SAA9730_LSR_THRE 0x20
+
+#endif /* !(SAA9730_UART_H) */
diff -u --recursive --new-file v2.4.9/linux/include/asm-mips64/mipsregs.h linux/include/asm-mips64/mipsregs.h
--- v2.4.9/linux/include/asm-mips64/mipsregs.h Wed Jul 25 17:10:25 2001
+++ linux/include/asm-mips64/mipsregs.h Sun Sep 9 10:43:02 2001
@@ -1,5 +1,4 @@
-/* $Id: mipsregs.h,v 1.1 1999/08/18 23:37:51 ralf Exp $
- *
+/*
X * This file is subject to the terms and conditions of the GNU General Public
X * License. See the file "COPYING" in the main directory of this archive
X * for more details.
@@ -34,6 +33,7 @@
X #define CP0_CONTEXT $4
X #define CP0_PAGEMASK $5
X #define CP0_WIRED $6
+#define CP0_INFO $7
X #define CP0_BADVADDR $8
X #define CP0_COUNT $9
X #define CP0_ENTRYHI $10
diff -u --recursive --new-file v2.4.9/linux/include/asm-mips64/mman.h linux/include/asm-mips64/mman.h
--- v2.4.9/linux/include/asm-mips64/mman.h Sat May 13 08:31:25 2000
+++ linux/include/asm-mips64/mman.h Sun Sep 9 10:43:02 2001
@@ -1,5 +1,4 @@
-/* $Id: mman.h,v 1.3 2000/02/04 23:12:27 ralf Exp $
- *
+/*
X * This file is subject to the terms and conditions of the GNU General Public
X * License. See the file "COPYING" in the main directory of this archive
X * for more details.
diff -u --recursive --new-file v2.4.9/linux/include/asm-mips64/mmu_context.h linux/include/asm-mips64/mmu_context.h
--- v2.4.9/linux/include/asm-mips64/mmu_context.h Thu Aug 10 13:30:05 2000
+++ linux/include/asm-mips64/mmu_context.h Sun Sep 9 10:43:02 2001
@@ -1,5 +1,4 @@
-/* $Id: mmu_context.h,v 1.4 2000/02/23 00:41:38 ralf Exp $
- *
+/*
X * Switch a MMU context.
X *
X * This file is subject to the terms and conditions of the GNU General Public
diff -u --recursive --new-file v2.4.9/linux/include/asm-mips64/module.h linux/include/asm-mips64/module.h
--- v2.4.9/linux/include/asm-mips64/module.h Tue Nov 7 10:46:04 2000
+++ linux/include/asm-mips64/module.h Sun Sep 9 10:43:02 2001
@@ -4,8 +4,64 @@
X * This file contains the mips64 architecture specific module code.
X */
X
+#include <linux/module.h>
+#include <asm/uaccess.h>
+
X #define module_map(x) vmalloc(x)
X #define module_unmap(x) vfree(x)
-#define module_arch_init(x) (0)
+#define module_arch_init(x) mips64_module_init(x)
+#define arch_init_modules(x) mips64_init_modules(x)
+
+/*
+ * This must match in size and layout the data created by
+ * modutils/obj/obj-mips64.c
+ */
+struct archdata {
+ const struct exception_table_entry *dbe_table_start;
+ const struct exception_table_entry *dbe_table_end;
+};
+
+static inline int
+mips64_module_init(struct module *mod)
+{
+ struct archdata *archdata;
+
+ if (!mod_member_present(mod, archdata_end))
+ return 0;
+
+ archdata = (struct archdata *)(mod->archdata_start);
+ if (!mod_archdata_member_present(mod, struct archdata, dbe_table_end))
+ return 0;
+
+ if (archdata->dbe_table_start > archdata->dbe_table_end ||
+ (archdata->dbe_table_start &&
+ !((unsigned long)archdata->dbe_table_start >=
+ ((unsigned long)mod + mod->size_of_struct) &&
+ ((unsigned long)archdata->dbe_table_end <
+ (unsigned long)mod + mod->size))) ||
+ (((unsigned long)archdata->dbe_table_start -
+ (unsigned long)archdata->dbe_table_end) %
+ sizeof(struct exception_table_entry))) {
+ printk(KERN_ERR
+ "module_arch_init: archdata->dbe_table_* invalid.\n");
+ return 1;
+ }
+
+ return 0;
+}
+
+static inline void
+mips64_init_modules(struct module *mod)
+{
+ extern const struct exception_table_entry __start___dbe_table[];
+ extern const struct exception_table_entry __stop___dbe_table[];
+ static struct archdata archdata = {
+ dbe_table_start: __start___dbe_table,
+ dbe_table_end: __stop___dbe_table,
+ };
+
+ mod->archdata_start = (char *)&archdata;
+ mod->archdata_end = mod->archdata_start + sizeof(archdata);
+}
X
X #endif /* _ASM_MIPS64_MODULE_H */
diff -u --recursive --new-file v2.4.9/linux/include/asm-mips64/namei.h linux/include/asm-mips64/namei.h
--- v2.4.9/linux/include/asm-mips64/namei.h Sat May 13 08:31:25 2000
+++ linux/include/asm-mips64/namei.h Sun Sep 9 10:43:02 2001
@@ -1,5 +1,4 @@
-/* $Id$
- *
+/*
X * This file is subject to the terms and conditions of the GNU General Public
X * License. See the file "COPYING" in the main directory of this archive
X * for more details.
diff -u --recursive --new-file v2.4.9/linux/include/asm-mips64/ng1.h linux/include/asm-mips64/ng1.h
--- v2.4.9/linux/include/asm-mips64/ng1.h Sat May 13 08:31:25 2000
+++ linux/include/asm-mips64/ng1.h Sun Sep 9 10:43:02 2001
@@ -1,5 +1,4 @@
-/* $Id$
- *
+/*
X * This file is subject to the terms and conditions of the GNU General Public
X * License. See the file "COPYING" in the main directory of this archive
X * for more details.
diff -u --recursive --new-file v2.4.9/linux/include/asm-mips64/paccess.h linux/include/asm-mips64/paccess.h
--- v2.4.9/linux/include/asm-mips64/paccess.h Sat May 13 08:31:25 2000
+++ linux/include/asm-mips64/paccess.h Sun Sep 9 10:43:02 2001
@@ -1,5 +1,4 @@
-/* $Id: paccess.h,v 1.2 2000/01/21 22:34:07 ralf Exp $
- *
+/*
X * This file is subject to the terms and conditions of the GNU General Public
X * License. See the file "COPYING" in the main directory of this archive
X * for more details.
diff -u --recursive --new-file v2.4.9/linux/include/asm-mips64/parport.h linux/include/asm-mips64/parport.h
--- v2.4.9/linux/include/asm-mips64/parport.h Sat May 13 08:31:25 2000
+++ linux/include/asm-mips64/parport.h Sun Sep 9 10:43:02 2001
@@ -1,5 +1,4 @@
-/* $Id$
- *
+/*
X * Copyright (C) 1999, 2000 Tim Waugh <t...@cyberelk.demon.co.uk>
X *
X * This file should only be included by drivers/parport/parport_pc.c.
diff -u --recursive --new-file v2.4.9/linux/include/asm-mips64/pci/bridge.h linux/include/asm-mips64/pci/bridge.h
--- v2.4.9/linux/include/asm-mips64/pci/bridge.h Fri Apr 13 20:26:07 2001
+++ linux/include/asm-mips64/pci/bridge.h Sun Sep 9 10:43:02 2001
@@ -1,5 +1,4 @@
-/* $Id$
- *
+/*
X * This file is subject to the terms and conditions of the GNU General Public
X * License. See the file "COPYING" in the main directory of this archive
X * for more details.
@@ -828,11 +827,11 @@
X
X #define BRIDGE_INTERNAL_ATES 128
X
-/* ========================================================================
- * Linux pci bus mappings to sn physical id's
+/*
+ * Linux pci bus mappings to sn physical id's
X */
-unsigned char bus_to_wid[256]; /* widget id for linux pci bus */
-unsigned char bus_to_nid[256]; /* nasid for linux pci bus */
-unsigned char num_bridges; /* number of bridges in the system */
+extern unsigned char bus_to_wid[]; /* widget id for linux pci bus */
+extern unsigned char bus_to_nid[]; /* nasid for linux pci bus */
+extern unsigned char num_bridges; /* number of bridges in the system */
X
X #endif /* _ASM_PCI_BRIDGE_H */
diff -u --recursive --new-file v2.4.9/linux/include/asm-mips64/pci.h linux/include/asm-mips64/pci.h
--- v2.4.9/linux/include/asm-mips64/pci.h Wed Jul 25 17:10:25 2001
+++ linux/include/asm-mips64/pci.h Sun Sep 9 10:43:02 2001
@@ -6,13 +6,19 @@
X #ifndef _ASM_PCI_H
X #define _ASM_PCI_H
X
+#include <linux/config.h>
+
X #ifdef __KERNEL__
X
X /* Can be used to override the logic in pci_scan_bus for skipping
X already-configured bus numbers - to be used for buggy BIOSes
X or architectures with incomplete PCI setup by the loader */
X
+#ifdef CONFIG_PCI
+extern unsigned int pcibios_assign_all_busses(void);
+#else
X #define pcibios_assign_all_busses() 0
+#endif
X
X #define PCIBIOS_MIN_IO 0x1000
X #define PCIBIOS_MIN_MEM 0x10000000
@@ -64,6 +70,24 @@
X extern void pci_free_consistent(struct pci_dev *hwdev, size_t size,
X void *vaddr, dma_addr_t dma_handle);
X
+
+#ifdef CONFIG_MAPPED_PCI_IO
+
+extern dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size,
+ int direction);
+extern void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr,
+ size_t size, int direction);
+extern int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents,
+ int direction);
+extern void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg,
+ int nents, int direction);
+extern void pci_dma_sync_single(struct pci_dev *hwdev, dma_addr_t dma_handle,
+ size_t size, int direction);
+extern void pci_dma_sync_sg(struct pci_dev *hwdev, struct scatterlist *sg,
+ int nelems, int direction);
+
+#else /* CONFIG_MAPPED_PCI_IO */
+
X /*
X * Map a single buffer of the indicated size for DMA in streaming mode.
X * The 32-bit bus address to use is returned.
@@ -71,7 +95,7 @@
X * Once the device is given the dma address, the device owns this memory
X * until either pci_unmap_single or pci_dma_sync_single is performed.
X */
-extern inline dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr,
+static inline dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr,
X size_t size, int direction)
X {
X if (direction == PCI_DMA_NONE)
@@ -80,7 +104,7 @@
X #ifndef CONFIG_COHERENT_IO
X dma_cache_wback_inv((unsigned long)ptr, size);
X #endif
- return (bus_to_baddr[hwdev->bus->number] | __pa(ptr));
+ return virt_to_bus(ptr);
X }
X
X /*
@@ -91,7 +115,7 @@
X * After this call, reads by the cpu to the buffer are guarenteed to see
X * whatever the device wrote there.
X */
-extern inline void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr,
+static inline void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr,
X size_t size, int direction)
X {
X if (direction == PCI_DMA_NONE)
@@ -116,7 +140,7 @@
X * Device ownership issues as mentioned above for pci_map_single are
X * the same here.
X */
-extern inline int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg,
+static inline int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg,
X int nents, int direction)
X {
X int i;
@@ -140,7 +164,7 @@
X * Again, cpu read rules concerning calls here are the same as for
X * pci_unmap_single() above.
X */
-extern inline void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg,
+static inline void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg,
X int nents, int direction)
X {
X if (direction == PCI_DMA_NONE)
@@ -159,7 +183,7 @@
X * next point you give the PCI dma address back to the card, the
X * device again owns the buffer.
X */
-extern inline void pci_dma_sync_single(struct pci_dev *hwdev,
+static inline void pci_dma_sync_single(struct pci_dev *hwdev,
X dma_addr_t dma_handle,
X size_t size, int direction)
X {
@@ -177,7 +201,7 @@
X * The same as pci_dma_sync_single but for a scatter-gather list,
X * same rules and usage.
X */
-extern inline void pci_dma_sync_sg(struct pci_dev *hwdev,
+static inline void pci_dma_sync_sg(struct pci_dev *hwdev,
X struct scatterlist *sg,
X int nelems, int direction)
X {
@@ -194,8 +218,9 @@
X dma_cache_wback_inv((unsigned long)sg->address, sg->length);
X #endif
X }
+#endif /* CONFIG_MAPPED_PCI_IO */
X
-extern inline int pci_dma_supported(struct pci_dev *hwdev, dma_addr_t mask)
+static inline int pci_dma_supported(struct pci_dev *hwdev, dma_addr_t mask)
X {
X /*
X * we fall back to GFP_DMA when the mask isn't all 1s,
@@ -208,7 +233,9 @@
X return 1;
X }
X
-/* Return the index of the PCI controller for device. */
+/*
+ * Return the index of the PCI controller for device.
+ */
X #define pci_controller_num(pdev) (0)
X
X /*
diff -u --recursive --new-file v2.4.9/linux/include/asm-mips64/pgtable.h linux/include/asm-mips64/pgtable.h
--- v2.4.9/linux/include/asm-mips64/pgtable.h Wed Jul 25 17:10:25 2001
+++ linux/include/asm-mips64/pgtable.h Sun Sep 9 10:43:02 2001
@@ -461,6 +461,23 @@
X }
X
X /*
+ * Macro to make mark a page protection value as "uncacheable". Note
+ * that "protection" is really a misnomer here as the protection value
+ * contains the memory attribute bits, dirty bits, and various other
+ * bits as well.
+ */
+#define pgprot_noncached pgprot_noncached
+
+static inline pgprot_t pgprot_noncached(pgprot_t _prot)
+{
+ unsigned long prot = pgprot_val(_prot);
+
+ prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
+
+ return __pgprot(prot);
+}
+
+/*
X * Conversion functions: convert a page and protection to a page entry,
X * and a page entry and page directory to the page they refer to.
X */
@@ -601,9 +618,9 @@
X {
X __asm__ __volatile__(
X ".set noreorder\n\t"
- "mtc0 %0, $5\n\t"
+ "mtc0 %z0, $5\n\t"
X ".set reorder"
- : : "r" (val));
+ : : "Jr" (val));
X }
X
X /* CP0_ENTRYLO0 and CP0_ENTRYLO1 registers */
@@ -623,9 +640,9 @@
X {
X __asm__ __volatile__(
X ".set noreorder\n\t"
- "dmtc0 %0, $2\n\t"
+ "dmtc0 %z0, $2\n\t"
X ".set reorder"
- : : "r" (val));
+ : : "Jr" (val));
X }
X
X extern inline unsigned long get_entrylo1(void)
@@ -644,9 +661,9 @@
X {
X __asm__ __volatile__(
X ".set noreorder\n\t"
- "dmtc0 %0, $3\n\t"
+ "dmtc0 %z0, $3\n\t"
X ".set reorder"
- : : "r" (val));
+ : : "Jr" (val));
X }
X
X /* CP0_ENTRYHI register */
@@ -667,9 +684,9 @@
X {
X __asm__ __volatile__(
X ".set noreorder\n\t"
- "dmtc0 %0, $10\n\t"
+ "dmtc0 %z0, $10\n\t"
X ".set reorder"
- : : "r" (val));
+ : : "Jr" (val));
X }
X
X /* CP0_INDEX register */
@@ -689,9 +706,9 @@
X {
X __asm__ __volatile__(
X ".set noreorder\n\t"
- "mtc0 %0, $0\n\t"
+ "mtc0 %z0, $0\n\t"
X ".set reorder\n\t"
- : : "r" (val));
+ : : "Jr" (val));
X }
X
X /* CP0_WIRED register */
@@ -711,9 +728,9 @@
X {
X __asm__ __volatile__(
X "\n\t.set noreorder\n\t"
- "mtc0 %0, $6\n\t"
+ "mtc0 %z0, $6\n\t"
X ".set reorder"
- : : "r" (val));
+ : : "Jr" (val));
X }
X
X extern inline unsigned long get_info(void)
@@ -746,9 +763,9 @@
X {
X __asm__ __volatile__(
X ".set noreorder\n\t"
- "mtc0 %0, $28\n\t"
+ "mtc0 %z0, $28\n\t"
X ".set reorder"
- : : "r" (val));
+ : : "Jr" (val));
X }
X
X extern inline unsigned long get_taghi(void)
@@ -767,9 +784,9 @@
X {
X __asm__ __volatile__(
X ".set noreorder\n\t"
- "mtc0 %0, $29\n\t"
+ "mtc0 %z0, $29\n\t"
X ".set reorder"
- : : "r" (val));
+ : : "Jr" (val));
X }
X
X /* CP0_CONTEXT register */
@@ -790,13 +807,18 @@
X {
X __asm__ __volatile__(
X ".set noreorder\n\t"
- "dmtc0 %0, $4\n\t"
+ "dmtc0 %z0, $4\n\t"
X ".set reorder"
- : : "r" (val));
+ : : "Jr" (val));
X }
X
X #include <asm-generic/pgtable.h>
X
X #endif /* !defined (_LANGUAGE_ASSEMBLY) */
+
+/*
+ * No page table caches to initialise
+ */
+#define pgtable_cache_init() do { } while (0)
X
X #endif /* _ASM_PGTABLE_H */
diff -u --recursive --new-file v2.4.9/linux/include/asm-mips64/poll.h linux/include/asm-mips64/poll.h
--- v2.4.9/linux/include/asm-mips64/poll.h Sat May 13 08:31:25 2000
+++ linux/include/asm-mips64/poll.h Sun Sep 9 10:43:02 2001
@@ -1,5 +1,4 @@
-/* $Id$
- *
+/*
X * This file is subject to the terms and conditions of the GNU General Public
X * License. See the file "COPYING" in the main directory of this archive
X * for more details.
diff -u --recursive --new-file v2.4.9/linux/include/asm-mips64/processor.h linux/include/asm-mips64/processor.h
--- v2.4.9/linux/include/asm-mips64/processor.h Wed Jul 25 17:10:25 2001
+++ linux/include/asm-mips64/processor.h Mon Sep 17 15:30:14 2001
@@ -198,9 +198,6 @@
X
X #endif /* !defined (_LANGUAGE_ASSEMBLY) */
X
-#define INIT_MMAP { &init_mm, KSEG0, KSEG1, NULL, PAGE_SHARED, \
- VM_READ | VM_WRITE | VM_EXEC, 1, NULL, NULL }
-
X #define INIT_THREAD { \
X /* \
X * saved main processor registers \
diff -u --recursive --new-file v2.4.9/linux/include/asm-mips64/r10kcache.h linux/include/asm-mips64/r10kcache.h
--- v2.4.9/linux/include/asm-mips64/r10kcache.h Sat May 13 08:31:25 2000
+++ linux/include/asm-mips64/r10kcache.h Sun Sep 9 10:43:02 2001
@@ -1,5 +1,4 @@
-/* $Id: r10kcache.h,v 1.1 2000/01/16 01:27:14 ralf Exp $
- *
+/*
X * This file is subject to the terms and conditions of the GNU General Public
X * License. See the file "COPYING" in the main directory of this archive
X * for more details.
diff -u --recursive --new-file v2.4.9/linux/include/asm-mips64/r10kcacheops.h linux/include/asm-mips64/r10kcacheops.h
--- v2.4.9/linux/include/asm-mips64/r10kcacheops.h Sat May 13 08:31:25 2000
+++ linux/include/asm-mips64/r10kcacheops.h Sun Sep 9 10:43:02 2001
@@ -1,5 +1,4 @@
-/* $Id: r10kcacheops.h,v 1.1 2000/01/12 23:18:32 ralf Exp $
- *
+/*
X * This file is subject to the terms and conditions of the GNU General Public
X * License. See the file "COPYING" in the main directory of this archive
X * for more details.
diff -u --recursive --new-file v2.4.9/linux/include/asm-mips64/r4kcache.h linux/include/asm-mips64/r4kcache.h
--- v2.4.9/linux/include/asm-mips64/r4kcache.h Sat May 13 08:31:25 2000
+++ linux/include/asm-mips64/r4kcache.h Sun Sep 9 10:43:02 2001
@@ -1,5 +1,4 @@
-/* $Id$
- *
+/*
X * This file is subject to the terms and conditions of the GNU General Public
X * License. See the file "COPYING" in the main directory of this archive
X * for more details.
diff -u --recursive --new-file v2.4.9/linux/include/asm-mips64/r4kcacheops.h linux/include/asm-mips64/r4kcacheops.h
--- v2.4.9/linux/include/asm-mips64/r4kcacheops.h Sat May 13 08:31:25 2000
+++ linux/include/asm-mips64/r4kcacheops.h Sun Sep 9 10:43:02 2001
SHAR_EOF
true || echo 'restore of patch-2.4.10 failed'
fi
echo 'End of part 180'
echo 'File patch-2.4.10 is continued in part 181'
echo "181" > _shar_seq_.tmp
exit 0