Linux Kernel Patch v2.4, patch-2.4.11 (06/77)
Thomas Kobienia
#!/bin/sh -x
# this is part 06 of a 77 - part archive
# do not concatenate these parts, unpack them in order with /bin/sh
# file patch-2.4.11 continued
if test ! -r _shar_seq_.tmp; then
echo 'Please unpack part 1 first!'
exit 1
fi
(read Scheck
if test "$Scheck" != 06; then
echo "Please unpack part $Scheck next!"
exit 1
else
exit 0
fi
) < _shar_seq_.tmp || exit 1
if test ! -f _shar_wnt_.tmp; then
echo 'x - still skipping patch-2.4.11'
else
echo 'x - continuing with patch-2.4.11'
sed 's/^X//' << 'SHAR_EOF' >> 'patch-2.4.11' &&
X while (cons) {
@@ -271,6 +280,10 @@
X register_console(cons);
X }
X restore_flags(flags);
+ /*
+ * Restore in-interrupt status for a resume from obp.
+ */
+ irq_enter(smp_processor_id(), 0);
X return 0;
X }
X
diff -u --recursive --new-file v2.4.10/linux/arch/sparc64/kernel/sparc64_ksyms.c linux/arch/sparc64/kernel/sparc64_ksyms.c
--- v2.4.10/linux/arch/sparc64/kernel/sparc64_ksyms.c Sun Sep 23 11:40:56 2001
+++ linux/arch/sparc64/kernel/sparc64_ksyms.c Mon Oct 1 09:19:56 2001
@@ -1,4 +1,4 @@
-/* $Id: sparc64_ksyms.c,v 1.111 2001/08/30 03:22:00 kanoj Exp $
+/* $Id: sparc64_ksyms.c,v 1.112 2001/09/25 23:30:23 davem Exp $
X * arch/sparc64/kernel/sparc64_ksyms.c: Sparc64 specific ksyms support.
X *
X * Copyright (C) 1996 David S. Miller (da...@caip.rutgers.edu)
@@ -278,6 +278,7 @@
X EXPORT_SYMBOL(strlen);
X EXPORT_SYMBOL(strnlen);
X EXPORT_SYMBOL(__strlen_user);
+EXPORT_SYMBOL(__strnlen_user);
X EXPORT_SYMBOL(strcpy);
X EXPORT_SYMBOL(strncpy);
X EXPORT_SYMBOL(strcat);
diff -u --recursive --new-file v2.4.10/linux/arch/sparc64/kernel/sys_sparc32.c linux/arch/sparc64/kernel/sys_sparc32.c
--- v2.4.10/linux/arch/sparc64/kernel/sys_sparc32.c Mon Aug 27 12:41:40 2001
+++ linux/arch/sparc64/kernel/sys_sparc32.c Mon Oct 1 09:19:56 2001
@@ -1,4 +1,4 @@
-/* $Id: sys_sparc32.c,v 1.178 2001/08/13 14:40:07 davem Exp $
+/* $Id: sys_sparc32.c,v 1.179 2001/09/25 00:48:09 davem Exp $
X * sys_sparc32.c: Conversion between 32bit and 64bit native syscalls.
X *
X * Copyright (C) 1997,1998 Jakub Jelinek (j...@sunsite.mff.cuni.cz)
@@ -4015,7 +4015,7 @@
X ret = sys_sendfile(out_fd, in_fd, offset ? &of : NULL, count);
X set_fs(old_fs);
X
- if (!ret && offset && put_user(of, offset))
+ if (offset && put_user(of, offset))
X return -EFAULT;
X
X return ret;
diff -u --recursive --new-file v2.4.10/linux/arch/sparc64/kernel/traps.c linux/arch/sparc64/kernel/traps.c
--- v2.4.10/linux/arch/sparc64/kernel/traps.c Sun Sep 23 11:40:56 2001
+++ linux/arch/sparc64/kernel/traps.c Mon Oct 1 09:19:56 2001
@@ -1,4 +1,4 @@
-/* $Id: traps.c,v 1.78 2001/09/14 19:49:32 kanoj Exp $
+/* $Id: traps.c,v 1.79 2001/09/21 02:14:39 kanoj Exp $
X * arch/sparc64/kernel/traps.c
X *
X * Copyright (C) 1995,1997 David S. Miller (da...@caip.rutgers.edu)
@@ -1636,44 +1636,6 @@
X {
X die_if_kernel("TL1: Tag Overflow Exception", regs);
X }
-
-#ifdef CONFIG_EC_FLUSH_TRAP
-void cache_flush_trap(struct pt_regs *regs)
-{
-#ifndef CONFIG_SMP
- unsigned node = linux_cpus[get_cpuid()].prom_node;
-#else
-#error cache_flush_trap not supported on sparc64/SMP yet
-#endif
-
-#if 0
-/* Broken */
- int size = prom_getintdefault(node, "ecache-size", 512*1024);
- int i, j;
- unsigned long addr;
- struct page *page, *end;
-
- regs->tpc = regs->tnpc;
- regs->tnpc = regs->tnpc + 4;
- if (!capable(CAP_SYS_ADMIN)) return;
- size >>= PAGE_SHIFT;
- addr = PAGE_OFFSET - PAGE_SIZE;
- page = mem_map - 1;
- end = mem_map + max_mapnr;
- for (i = 0; i < size; i++) {
- do {
- addr += PAGE_SIZE;
- page++;
- if (page >= end)
- return;
- } while (!PageReserved(page));
- /* E-Cache line size is 64B. Let us pollute it :)) */
- for (j = 0; j < PAGE_SIZE; j += 64)
- __asm__ __volatile__ ("ldx [%0 + %1], %%g1" : : "r" (j), "r" (addr) : "g1");
- }
-#endif
-}
-#endif
X
X void do_getpsr(struct pt_regs *regs)
X {
diff -u --recursive --new-file v2.4.10/linux/arch/sparc64/kernel/ttable.S linux/arch/sparc64/kernel/ttable.S
--- v2.4.10/linux/arch/sparc64/kernel/ttable.S Mon Aug 27 12:41:40 2001
+++ linux/arch/sparc64/kernel/ttable.S Mon Oct 1 09:19:56 2001
@@ -1,4 +1,4 @@
-/* $Id: ttable.S,v 1.34 2001/08/12 09:08:56 davem Exp $
+/* $Id: ttable.S,v 1.35 2001/09/21 02:14:39 kanoj Exp $
X * ttable.S: Sparc V9 Trap Table(s) with SpitFire/Cheetah extensions.
X *
X * Copyright (C) 1996, 2001 David S. Miller (da...@caip.rutgers.edu)
@@ -144,12 +144,7 @@
X tl0_resv169: BTRAP(0x169) BTRAP(0x16a) BTRAP(0x16b) BTRAP(0x16c)
X tl0_linux64: LINUX_64BIT_SYSCALL_TRAP
X tl0_gsctx: TRAP(sparc64_get_context) TRAP(sparc64_set_context)
-tl0_resv170: BTRAP(0x170) BTRAP(0x171)
-#ifdef CONFIG_EC_FLUSH_TRAP
- TRAP(cache_flush_trap)
-#else
- BTRAP(0x172)
-#endif
+tl0_resv170: BTRAP(0x170) BTRAP(0x171) BTRAP(0x172)
X tl0_resv173: BTRAP(0x173) BTRAP(0x174) BTRAP(0x175) BTRAP(0x176) BTRAP(0x177)
X tl0_resv178: BTRAP(0x178) BTRAP(0x179) BTRAP(0x17a) BTRAP(0x17b) BTRAP(0x17c)
X tl0_resv17d: BTRAP(0x17d) BTRAP(0x17e) BTRAP(0x17f)
diff -u --recursive --new-file v2.4.10/linux/arch/sparc64/lib/VIScopy.S linux/arch/sparc64/lib/VIScopy.S
--- v2.4.10/linux/arch/sparc64/lib/VIScopy.S Thu Nov 9 15:57:41 2000
+++ linux/arch/sparc64/lib/VIScopy.S Mon Oct 1 09:19:56 2001
@@ -1,4 +1,4 @@
-/* $Id: VIScopy.S,v 1.25 2000/11/01 09:29:19 davem Exp $
+/* $Id: VIScopy.S,v 1.26 2001/09/27 04:36:24 kanoj Exp $
X * VIScopy.S: High speed copy operations utilizing the UltraSparc
X * Visual Instruction Set.
X *
@@ -310,17 +310,6 @@
X .globl __memcpy
X .type __memcpy,@function
X
- .globl __memcpy_384plus
- .type __memcpy_384plus,@function
-
- .globl __memcpy_16plus
- .type __memcpy_16plus,@function
-
- .globl __memcpy_short
- .type __memcpy_short,@function
-
- .globl __memcpy_entry
- .type __memcpy_entry,@function
X memcpy_private:
X __memcpy:
X memcpy: mov ASI_P, asi_src ! IEU0 Group
@@ -395,7 +384,6 @@
X
X .align 32
X #ifdef __KERNEL__
-__memcpy_384plus:
X andcc %o0, 7, %g2 ! IEU1 Group
X #endif
X VIS_enter:
@@ -735,9 +723,6 @@
X bleu,pn %xcc, __memcpy_short ! CTI
X cmp %o2, (64 * 6) ! IEU1 Group
X bgeu,pn %xcc, VIS_enter ! CTI
-#ifdef __KERNEL__
-__memcpy_16plus:
-#endif
X andcc %o0, 7, %g2 ! IEU1 Group
X sub %o0, %o1, %g5 ! IEU0
X andcc %g5, 3, %o5 ! IEU1 Group
diff -u --recursive --new-file v2.4.10/linux/arch/sparc64/lib/blockops.S linux/arch/sparc64/lib/blockops.S
--- v2.4.10/linux/arch/sparc64/lib/blockops.S Sun Sep 23 11:40:56 2001
+++ linux/arch/sparc64/lib/blockops.S Mon Oct 1 09:19:56 2001
@@ -1,4 +1,4 @@
-/* $Id: blockops.S,v 1.35 2001/09/04 16:39:53 kanoj Exp $
+/* $Id: blockops.S,v 1.36 2001/09/24 21:44:03 davem Exp $
X * blockops.S: UltraSparc block zero optimized routines.
X *
X * Copyright (C) 1996, 1998, 1999, 2000 David S. Miller (da...@redhat.com)
@@ -25,7 +25,7 @@
X
X #if (PAGE_SHIFT == 13) || (PAGE_SHIFT == 19)
X #define PAGE_SIZE_REM 0x80
-#elif (PAGE_SHIFT == 16) || (PAGE_SHIFT == 21)
+#elif (PAGE_SHIFT == 16) || (PAGE_SHIFT == 22)
X #define PAGE_SIZE_REM 0x100
X #else
X #error Wrong PAGE_SHIFT specified
@@ -64,7 +64,7 @@
X cmp %o2, PAGE_SIZE_REM
X bne,pt %xcc, 1b
X add %o0, 0x40, %o0
-#if (PAGE_SHIFT == 16) || (PAGE_SHIFT == 21)
+#if (PAGE_SHIFT == 16) || (PAGE_SHIFT == 22)
X TOUCH(f0, f2, f4, f6, f8, f10, f12, f14)
X ldda [%o1] ASI_BLK_P, %f32
X stda %f48, [%o0] ASI_BLK_P
@@ -287,7 +287,7 @@
X cmp %o2, PAGE_SIZE_REM
X bne,pt %xcc, 1b
X add %o0, 0x40, %o0
-#if (PAGE_SHIFT == 16) || (PAGE_SHIFT == 21)
+#if (PAGE_SHIFT == 16) || (PAGE_SHIFT == 22)
X TOUCH(f0, f2, f4, f6, f8, f10, f12, f14)
X ldda [%o1] ASI_BLK_P, %f32
X stda %f48, [%o0] ASI_BLK_P
@@ -353,7 +353,7 @@
X cmp %o2, PAGE_SIZE_REM
X bne,pt %xcc, 1b
X add %o0, 0x40, %o0
-#if (PAGE_SHIFT == 16) || (PAGE_SHIFT == 21)
+#if (PAGE_SHIFT == 16) || (PAGE_SHIFT == 22)
X TOUCH(f0, f2, f4, f6, f8, f10, f12, f14)
X ldda [%o1] ASI_BLK_P, %f32
X stda %f48, [%o0] ASI_BLK_COMMIT_P
diff -u --recursive --new-file v2.4.10/linux/arch/sparc64/mm/init.c linux/arch/sparc64/mm/init.c
--- v2.4.10/linux/arch/sparc64/mm/init.c Sun Sep 23 11:40:56 2001
+++ linux/arch/sparc64/mm/init.c Mon Oct 1 09:19:56 2001
@@ -1,4 +1,4 @@
-/* $Id: init.c,v 1.189 2001/09/02 23:27:18 kanoj Exp $
+/* $Id: init.c,v 1.193 2001/09/25 22:47:35 davem Exp $
X * arch/sparc64/mm/init.c
X *
X * Copyright (C) 1996-1999 David S. Miller (da...@caip.rutgers.edu)
@@ -30,6 +30,7 @@
X #include <asm/dma.h>
X #include <asm/starfire.h>
X #include <asm/tlb.h>
+#include <asm/spitfire.h>
X
X mmu_gather_t mmu_gathers[NR_CPUS];
X
@@ -113,16 +114,17 @@
X
X if (VALID_PAGE(page) && page->mapping &&
X test_bit(PG_dcache_dirty, &page->flags)) {
- __flush_dcache_page(page->virtual,
- (tlb_type == spitfire));
+#if (L1DCACHE_SIZE > PAGE_SIZE) /* is there D$ aliasing problem */
+ __flush_dcache_page(page->virtual, (tlb_type == spitfire));
+#else
+ if (tlb_type == spitfire) /* fix local I$ coherency */
+ __flush_icache_page(__get_phys((unsigned long)(page->virtual)));
+#endif
X clear_bit(PG_dcache_dirty, &page->flags);
X }
X __update_mmu_cache(vma, address, pte);
X }
X
-/* In arch/sparc64/mm/ultra.S */
-extern void __flush_icache_page(unsigned long);
-
X void flush_icache_range(unsigned long start, unsigned long end)
X {
X /* Cheetah has coherent I-cache. */
@@ -887,23 +889,28 @@
X * addresses. The idea is that if the vpte color and PAGE_OFFSET range
X * color is the same, then when the kernel initializes the pagetable
X * using the later address range, accesses with the first address
- * range will not see the newly initialized data rather than the
- * garbage.
+ * range will see the newly initialized data rather than the garbage.
X */
-
+#if (L1DCACHE_SIZE > PAGE_SIZE) /* is there D$ aliasing problem */
+#define DC_ALIAS_SHIFT 1
+#else
+#define DC_ALIAS_SHIFT 0
+#endif
X pte_t *pte_alloc_one(struct mm_struct *mm, unsigned long address)
X {
- struct page *page = alloc_pages(GFP_KERNEL, 1);
- unsigned long color = ((address >> (PAGE_SHIFT + 10)) & 1UL);
+ struct page *page = alloc_pages(GFP_KERNEL, DC_ALIAS_SHIFT);
+ unsigned long color = VPTE_COLOR(address);
X
X if (page) {
X unsigned long *to_free;
X unsigned long paddr;
X pte_t *pte;
X
+#if (L1DCACHE_SIZE > PAGE_SIZE) /* is there D$ aliasing problem */
X set_page_count((page + 1), 1);
+#endif
X paddr = (unsigned long) page_address(page);
- memset((char *)paddr, 0, (PAGE_SIZE << 1));
+ memset((char *)paddr, 0, (PAGE_SIZE << DC_ALIAS_SHIFT));
X
X if (!color) {
X pte = (pte_t *) paddr;
@@ -913,10 +920,12 @@
X to_free = (unsigned long *) paddr;
X }
X
+#if (L1DCACHE_SIZE > PAGE_SIZE) /* is there D$ aliasing problem */
X /* Now free the other one up, adjust cache size. */
X *to_free = (unsigned long) pte_quicklist[color ^ 0x1];
X pte_quicklist[color ^ 0x1] = to_free;
X pgtable_cache_size++;
+#endif
X
X return pte;
X }
diff -u --recursive --new-file v2.4.10/linux/arch/sparc64/mm/ultra.S linux/arch/sparc64/mm/ultra.S
--- v2.4.10/linux/arch/sparc64/mm/ultra.S Sun Sep 23 11:40:56 2001
+++ linux/arch/sparc64/mm/ultra.S Mon Oct 1 09:19:56 2001
@@ -1,4 +1,4 @@
-/* $Id: ultra.S,v 1.57 2001/09/06 19:27:17 kanoj Exp $
+/* $Id: ultra.S,v 1.61 2001/09/25 18:04:51 kanoj Exp $
X * ultra.S: Don't expand these all over the place...
X *
X * Copyright (C) 1997, 2000 David S. Miller (da...@redhat.com)
@@ -237,6 +237,16 @@
X retl
X /*IC22*/ wrpr %g1, 0x0, %pstate
X
+/*
+ * The following code flushes one page_size worth.
+ */
+#if (PAGE_SHIFT == 13)
+#define ITAG_MASK 0xfe
+#elif (PAGE_SHIFT == 16)
+#define ITAG_MASK 0x7fe
+#else
+#error unsupported PAGE_SIZE
+#endif
X .align 32
X .globl __flush_icache_page
X __flush_icache_page: /* %o0 = phys_page */
@@ -250,7 +260,7 @@
X or %o0, %g1, %o0 ! VALID+phys-addr comparitor
X
X sllx %g2, 1, %g2
- andn %g2, 0xfe, %g2 ! IC_tag mask
+ andn %g2, ITAG_MASK, %g2 ! IC_tag mask
X nop
X nop
X nop
@@ -313,6 +323,16 @@
X retl
X nop
X
+#if (PAGE_SHIFT == 13)
+#define DTAG_MASK 0x3
+#elif (PAGE_SHIFT == 16)
+#define DTAG_MASK 0x1f
+#elif (PAGE_SHIFT == 19)
+#define DTAG_MASK 0xff
+#elif (PAGE_SHIFT == 22)
+#define DTAG_MASK 0x3ff
+#endif
+
X flush_dcpage_spitfire:
X clr %o4
X srlx %o0, 11, %o0
@@ -323,19 +343,19 @@
X add %o4, (1 << 5), %o4 ! IEU0
X ldxa [%o4] ASI_DCACHE_TAG, %g2 ! LSU Group o3 available
X add %o4, (1 << 5), %o4 ! IEU0
- andn %o3, 0x3, %o3 ! IEU1
+ andn %o3, DTAG_MASK, %o3 ! IEU1
X ldxa [%o4] ASI_DCACHE_TAG, %g3 ! LSU Group
X add %o4, (1 << 5), %o4 ! IEU0
- andn %g1, 0x3, %g1 ! IEU1
+ andn %g1, DTAG_MASK, %g1 ! IEU1
X cmp %o0, %o3 ! IEU1 Group
X be,a,pn %xcc, dflush1 ! CTI
X sub %o4, (4 << 5), %o4 ! IEU0 (Group)
X cmp %o0, %g1 ! IEU1 Group
- andn %g2, 0x3, %g2 ! IEU0
+ andn %g2, DTAG_MASK, %g2 ! IEU0
X be,a,pn %xcc, dflush2 ! CTI
X sub %o4, (3 << 5), %o4 ! IEU0 (Group)
X cmp %o0, %g2 ! IEU1 Group
- andn %g3, 0x3, %g3 ! IEU0
+ andn %g3, DTAG_MASK, %g3 ! IEU0
X be,a,pn %xcc, dflush3 ! CTI
X sub %o4, (2 << 5), %o4 ! IEU0 (Group)
X cmp %o0, %g3 ! IEU1 Group
diff -u --recursive --new-file v2.4.10/linux/arch/sparc64/prom/misc.c linux/arch/sparc64/prom/misc.c
--- v2.4.10/linux/arch/sparc64/prom/misc.c Wed Jul 5 22:15:25 2000
+++ linux/arch/sparc64/prom/misc.c Mon Oct 1 09:19:56 2001
@@ -1,4 +1,4 @@
-/* $Id: misc.c,v 1.19 2000/06/30 10:18:38 davem Exp $
+/* $Id: misc.c,v 1.20 2001/09/21 03:17:07 kanoj Exp $
X * misc.c: Miscellaneous prom functions that don't belong
X * anywhere else.
X *
@@ -59,25 +59,15 @@
X prom_palette (1);
X #endif
X
- /* We always arrive here via a serial interrupt.
- * So in order for everything to work reliably, even
- * on SMP, we need to drop the IRQ locks we hold.
- */
X #ifdef CONFIG_SMP
- irq_exit(smp_processor_id(), 0);
X smp_capture();
-#else
- local_irq_count(smp_processor_id())--;
X #endif
X
X p1275_cmd ("enter", P1275_INOUT(0,0));
X
X #ifdef CONFIG_SMP
X smp_release();
- irq_enter(smp_processor_id(), 0);
X spin_unlock_wait(&__br_write_locks[BR_GLOBALIRQ_LOCK].lock);
-#else
- local_irq_count(smp_processor_id())++;
X #endif
X
X #ifdef CONFIG_SUN_CONSOLE
diff -u --recursive --new-file v2.4.10/linux/drivers/block/genhd.c linux/drivers/block/genhd.c
--- v2.4.10/linux/drivers/block/genhd.c Sun Sep 23 11:40:57 2001
+++ linux/drivers/block/genhd.c Mon Oct 1 10:19:22 2001
@@ -47,9 +47,27 @@
X void
X add_gendisk(struct gendisk *gp)
X {
+ struct gendisk *sgp;
+
X write_lock(&gendisk_lock);
+
+ /*
+ * In 2.5 this will go away. Fix the drivers who rely on
+ * old behaviour.
+ */
+
+ for (sgp = gendisk_head; sgp; sgp = sgp->next)
+ {
+ if (sgp == gp)
+ {
+// printk(KERN_ERR "add_gendisk: device major %d is buggy and added a live gendisk!\n",
+// sgp->major)
+ goto out;
+ }
+ }
X gp->next = gendisk_head;
X gendisk_head = gp;
+out:
X write_unlock(&gendisk_lock);
X }
X
diff -u --recursive --new-file v2.4.10/linux/drivers/block/loop.c linux/drivers/block/loop.c
--- v2.4.10/linux/drivers/block/loop.c Sun Sep 23 11:40:57 2001
+++ linux/drivers/block/loop.c Fri Sep 28 11:21:40 2001
@@ -719,7 +719,7 @@
X return err;
X }
X
-static int loop_clr_fd(struct loop_device *lo, kdev_t dev)
+static int loop_clr_fd(struct loop_device *lo, struct block_device *bdev)
X {
X struct file *filp = lo->lo_backing_file;
X int gfp = lo->old_gfp_mask;
@@ -752,7 +752,7 @@
X memset(lo->lo_encrypt_key, 0, LO_KEY_SIZE);
X memset(lo->lo_name, 0, LO_NAME_SIZE);
X loop_sizes[lo->lo_number] = 0;
- invalidate_buffers(dev);
+ invalidate_bdev(bdev, 0);
X filp->f_dentry->d_inode->i_mapping->gfp_mask = gfp;
X lo->lo_state = Lo_unbound;
X fput(filp);
@@ -852,7 +852,7 @@
X err = loop_set_fd(lo, file, inode->i_rdev, arg);
X break;
X case LOOP_CLR_FD:
- err = loop_clr_fd(lo, inode->i_rdev);
+ err = loop_clr_fd(lo, inode->i_bdev);
X break;
X case LOOP_SET_STATUS:
X err = loop_set_status(lo, (struct loop_info *) arg);
diff -u --recursive --new-file v2.4.10/linux/drivers/block/paride/Makefile linux/drivers/block/paride/Makefile
--- v2.4.10/linux/drivers/block/paride/Makefile Fri Apr 6 10:42:55 2001
+++ linux/drivers/block/paride/Makefile Fri Oct 5 12:06:51 2001
@@ -7,6 +7,8 @@
X
X L_TARGET := paride.a
X
+export-objs := bpck6.o
+
X obj-$(CONFIG_PARIDE) += paride.o
X obj-$(CONFIG_PARIDE_PD) += pd.o
X obj-$(CONFIG_PARIDE_PCD) += pcd.o
diff -u --recursive --new-file v2.4.10/linux/drivers/block/paride/bpck6.c linux/drivers/block/paride/bpck6.c
--- v2.4.10/linux/drivers/block/paride/bpck6.c Sun Sep 23 11:40:57 2001
+++ linux/drivers/block/paride/bpck6.c Fri Oct 5 12:06:51 2001
@@ -25,7 +25,6 @@
X
X #define BACKPACK_VERSION "2.0.2"
X
-#define EXPORT_SYMTAB
X #include <linux/module.h>
X #include <linux/kernel.h>
X #include <linux/slab.h>
diff -u --recursive --new-file v2.4.10/linux/drivers/block/paride/paride.c linux/drivers/block/paride/paride.c
--- v2.4.10/linux/drivers/block/paride/paride.c Fri Apr 6 10:42:55 2001
+++ linux/drivers/block/paride/paride.c Mon Oct 8 11:54:10 2001
@@ -44,7 +44,7 @@
X
X static struct pi_protocol *protocols[MAX_PROTOS];
X
-spinlock_t pi_spinlock = SPIN_LOCK_UNLOCKED;
+static spinlock_t pi_spinlock = SPIN_LOCK_UNLOCKED;
X
X void pi_write_regr( PIA *pi, int cont, int regr, int val)
X
diff -u --recursive --new-file v2.4.10/linux/drivers/block/rd.c linux/drivers/block/rd.c
--- v2.4.10/linux/drivers/block/rd.c Sun Sep 23 11:40:57 2001
+++ linux/drivers/block/rd.c Mon Oct 8 11:25:14 2001
@@ -276,7 +276,6 @@
X if (!Page_Uptodate(page)) {
X memset(kmap(page), 0, PAGE_CACHE_SIZE);
X kunmap(page);
- flush_dcache_page(page);
X SetPageUptodate(page);
X }
X
@@ -301,8 +300,11 @@
X kunmap(page);
X bh_kunmap(sbh);
X
- if (rw != READ)
+ if (rw == READ) {
+ flush_dcache_page(page);
+ } else {
X SetPageDirty(page);
+ }
X if (unlock)
X UnlockPage(page);
X __free_page(page);
diff -u --recursive --new-file v2.4.10/linux/drivers/char/Config.in linux/drivers/char/Config.in
--- v2.4.10/linux/drivers/char/Config.in Sun Sep 23 11:40:57 2001
+++ linux/drivers/char/Config.in Fri Oct 5 12:13:50 2001
@@ -205,8 +205,8 @@
X
X dep_tristate '/dev/agpgart (AGP Support)' CONFIG_AGP $CONFIG_DRM_AGP
X if [ "$CONFIG_AGP" != "n" ]; then
- bool ' Intel 440LX/BX/GX and I815/I840/I850 support' CONFIG_AGP_INTEL
- bool ' Intel I810/I815 (on-board) support' CONFIG_AGP_I810
+ bool ' Intel 440LX/BX/GX and I815/I830M/I840/I850 support' CONFIG_AGP_INTEL
+ bool ' Intel I810/I815/I830M (on-board) support' CONFIG_AGP_I810
X bool ' VIA chipset support' CONFIG_AGP_VIA
X bool ' AMD Irongate, 761, and 762 support' CONFIG_AGP_AMD
X bool ' Generic SiS support' CONFIG_AGP_SIS
diff -u --recursive --new-file v2.4.10/linux/drivers/char/Makefile linux/drivers/char/Makefile
--- v2.4.10/linux/drivers/char/Makefile Sun Sep 23 11:40:57 2001
+++ linux/drivers/char/Makefile Mon Oct 8 10:46:20 2001
@@ -23,7 +23,7 @@
X
X export-objs := busmouse.o console.o keyboard.o sysrq.o \
X misc.o pty.o random.o selection.o serial.o \
- sonypi.o tty_io.o tty_ioctl.o
+ sonypi.o tty_io.o tty_ioctl.o generic_serial.o
X
X mod-subdirs := joystick ftape drm pcmcia
X
diff -u --recursive --new-file v2.4.10/linux/drivers/char/agp/agp.h linux/drivers/char/agp/agp.h
--- v2.4.10/linux/drivers/char/agp/agp.h Sun Sep 23 11:40:57 2001
+++ linux/drivers/char/agp/agp.h Fri Oct 5 12:13:50 2001
@@ -133,6 +133,10 @@
X #define INREG16(mmap, addr) __raw_readw((mmap)+(addr))
X #define INREG8(mmap, addr) __raw_readb((mmap)+(addr))
X
+#define KB(x) ((x) * 1024)
+#define MB(x) (KB (KB (x)))
+#define GB(x) (MB (KB (x)))
+
X #define CACHE_FLUSH agp_bridge.cache_flush
X #define A_SIZE_8(x) ((aper_size_info_8 *) x)
X #define A_SIZE_16(x) ((aper_size_info_16 *) x)
@@ -196,6 +200,12 @@
X #ifndef PCI_DEVICE_ID_INTEL_815_1
X #define PCI_DEVICE_ID_INTEL_815_1 0x1132
X #endif
+#ifndef PCI_DEVICE_ID_INTEL_830_M_0
+#define PCI_DEVICE_ID_INTEL_830_M_0 0x3575
+#endif
+#ifndef PCI_DEVICE_ID_INTEL_830_M_1
+#define PCI_DEVICE_ID_INTEL_830_M_1 0x3577
+#endif
X #ifndef PCI_DEVICE_ID_INTEL_82443GX_1
X #define PCI_DEVICE_ID_INTEL_82443GX_1 0x71a1
X #endif
@@ -266,6 +276,22 @@
X #define I810_DRAM_CTL 0x3000
X #define I810_DRAM_ROW_0 0x00000001
X #define I810_DRAM_ROW_0_SDRAM 0x00000001
+
+/* intel i830 registers */
+#define I830_GMCH_CTRL 0x52
+#define I830_GMCH_ENABLED 0x4
+#define I830_GMCH_MEM_MASK 0x1
+#define I830_GMCH_MEM_64M 0x1
+#define I830_GMCH_MEM_128M 0
+#define I830_GMCH_GMS_MASK 0x70
+#define I830_GMCH_GMS_DISABLED 0x00
+#define I830_GMCH_GMS_LOCAL 0x10
+#define I830_GMCH_GMS_STOLEN_512 0x20
+#define I830_GMCH_GMS_STOLEN_1024 0x30
+#define I830_GMCH_GMS_STOLEN_8192 0x40
+#define I830_RDRAM_CHANNEL_TYPE 0x03010
+#define I830_RDRAM_ND(x) (((x) & 0x20) >> 5)
+#define I830_RDRAM_DDT(x) (((x) & 0x18) >> 3)
X
X /* VIA register */
X #define VIA_APBASE 0x10
diff -u --recursive --new-file v2.4.10/linux/drivers/char/agp/agpgart_be.c linux/drivers/char/agp/agpgart_be.c
--- v2.4.10/linux/drivers/char/agp/agpgart_be.c Sun Sep 23 11:40:57 2001
+++ linux/drivers/char/agp/agpgart_be.c Fri Oct 5 13:25:14 2001
@@ -1113,6 +1113,290 @@
X return 0;
X }
X
+static aper_size_info_fixed intel_i830_sizes[] =
+{
+ {128, 32768, 5},
+ /* The 64M mode still requires a 128k gatt */
+ {64, 16384, 5}
+};
+
+static struct _intel_i830_private {
+ struct pci_dev *i830_dev; /* device one */
+ volatile u8 *registers;
+ int gtt_entries;
+} intel_i830_private;
+
+static void intel_i830_init_gtt_entries(void) {
+ u16 gmch_ctrl;
+ int gtt_entries;
+ u8 rdct;
+ static const int ddt[4] = { 0, 16, 32, 64 };
+
+ pci_read_config_word(agp_bridge.dev,I830_GMCH_CTRL,&gmch_ctrl);
+
+ switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
+ case I830_GMCH_GMS_STOLEN_512:
+ gtt_entries = KB(512);
+ printk(KERN_INFO PFX "detected %dK stolen memory.\n",gtt_entries / KB(1));
+ break;
+ case I830_GMCH_GMS_STOLEN_1024:
+ gtt_entries = MB(1);
+ printk(KERN_INFO PFX "detected %dK stolen memory.\n",gtt_entries / KB(1));
+ break;
+ case I830_GMCH_GMS_STOLEN_8192:
+ gtt_entries = MB(8);
+ printk(KERN_INFO PFX "detected %dK stolen memory.\n",gtt_entries / KB(1));
+ break;
+ case I830_GMCH_GMS_LOCAL:
+ rdct = INREG8(intel_i830_private.registers,I830_RDRAM_CHANNEL_TYPE);
+ gtt_entries = (I830_RDRAM_ND(rdct) + 1) * MB(ddt[I830_RDRAM_DDT(rdct)]);
+ printk(KERN_INFO PFX "detected %dK local memory.\n",gtt_entries / KB(1));
+ break;
+ default:
+ printk(KERN_INFO PFX "no video memory detected.\n");
+ gtt_entries = 0;
+ break;
+ }
+
+ gtt_entries /= KB(4);
+
+ intel_i830_private.gtt_entries = gtt_entries;
+}
+
+/* The intel i830 automatically initializes the agp aperture during POST.
+ * Use the memory already set aside for in the GTT.
+ */
+static int intel_i830_create_gatt_table(void)
+{
+ int page_order;
+ aper_size_info_fixed *size;
+ int num_entries;
+ u32 temp;
+
+ size = agp_bridge.current_size;
+ page_order = size->page_order;
+ num_entries = size->num_entries;
+ agp_bridge.gatt_table_real = 0;
+
+ pci_read_config_dword(intel_i830_private.i830_dev,I810_MMADDR,&temp);
+ temp &= 0xfff80000;
+
+ intel_i830_private.registers = (volatile u8 *) ioremap(temp,128 * 4096);
+ if (!intel_i830_private.registers) return (-ENOMEM);
+
+ temp = INREG32(intel_i830_private.registers,I810_PGETBL_CTL) & 0xfffff000;
+ CACHE_FLUSH();
+
+ /* we have to call this as early as possible after the MMIO base address is known */
+ intel_i830_init_gtt_entries();
+
+ agp_bridge.gatt_table = NULL;
+
+ agp_bridge.gatt_bus_addr = temp;
+
+ return(0);
+}
+
+/* Return the gatt table to a sane state. Use the top of stolen
+ * memory for the GTT.
+ */
+static int intel_i830_free_gatt_table(void)
+{
+ return(0);
+}
+
+static int intel_i830_fetch_size(void)
+{
+ u16 gmch_ctrl;
+ aper_size_info_fixed *values;
+
+ pci_read_config_word(agp_bridge.dev,I830_GMCH_CTRL,&gmch_ctrl);
+ values = A_SIZE_FIX(agp_bridge.aperture_sizes);
+
+ if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
+ agp_bridge.previous_size = agp_bridge.current_size = (void *) values;
+ agp_bridge.aperture_size_idx = 0;
+ return(values[0].size);
+ } else {
+ agp_bridge.previous_size = agp_bridge.current_size = (void *) values;
+ agp_bridge.aperture_size_idx = 1;
+ return(values[1].size);
+ }
+
+ return(0);
+}
+
+static int intel_i830_configure(void)
+{
+ aper_size_info_fixed *current_size;
+ u32 temp;
+ u16 gmch_ctrl;
+ int i;
+
+ current_size = A_SIZE_FIX(agp_bridge.current_size);
+
+ pci_read_config_dword(intel_i830_private.i830_dev,I810_GMADDR,&temp);
+ agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+
+ pci_read_config_word(agp_bridge.dev,I830_GMCH_CTRL,&gmch_ctrl);
+ gmch_ctrl |= I830_GMCH_ENABLED;
+ pci_write_config_word(agp_bridge.dev,I830_GMCH_CTRL,gmch_ctrl);
+
+ OUTREG32(intel_i830_private.registers,I810_PGETBL_CTL,agp_bridge.gatt_bus_addr | I810_PGETBL_ENABLED);
+ CACHE_FLUSH();
+
+ if (agp_bridge.needs_scratch_page == TRUE)
+ for (i = intel_i830_private.gtt_entries; i < current_size->num_entries; i++)
+ OUTREG32(intel_i830_private.registers,I810_PTE_BASE + (i * 4),agp_bridge.scratch_page);
+
+ return (0);
+}
+
+static void intel_i830_cleanup(void)
+{
+ iounmap((void *) intel_i830_private.registers);
+}
+
+static int intel_i830_insert_entries(agp_memory *mem,off_t pg_start,int type)
+{
+ int i,j,num_entries;
+ void *temp;
+
+ temp = agp_bridge.current_size;
+ num_entries = A_SIZE_FIX(temp)->num_entries;
+
+ if (pg_start < intel_i830_private.gtt_entries) {
+ printk (KERN_DEBUG "pg_start == 0x%.8lx,intel_i830_private.gtt_entries == 0x%.8x\n",
+ pg_start,intel_i830_private.gtt_entries);
+
+ printk ("Trying to insert into local/stolen memory\n");
+ return (-EINVAL);
+ }
+
+ if ((pg_start + mem->page_count) > num_entries)
+ return (-EINVAL);
+
+ /* The i830 can't check the GTT for entries since its read only,
+ * depend on the caller to make the correct offset decisions.
+ */
+
+ if ((type != 0 && type != AGP_PHYS_MEMORY) ||
+ (mem->type != 0 && mem->type != AGP_PHYS_MEMORY))
+ return (-EINVAL);
+
+ CACHE_FLUSH();
+
+ for (i = 0, j = pg_start; i < mem->page_count; i++, j++)
+ OUTREG32(intel_i830_private.registers,I810_PTE_BASE + (j * 4),mem->memory[i]);
+
+ CACHE_FLUSH();
+
+ agp_bridge.tlb_flush(mem);
+
+ return(0);
+}
+
+static int intel_i830_remove_entries(agp_memory *mem,off_t pg_start,int type)
+{
+ int i;
+
+ CACHE_FLUSH ();
+
+ if (pg_start < intel_i830_private.gtt_entries) {
+ printk ("Trying to disable local/stolen memory\n");
+ return (-EINVAL);
+ }
+
+ for (i = pg_start; i < (mem->page_count + pg_start); i++)
+ OUTREG32(intel_i830_private.registers,I810_PTE_BASE + (i * 4),agp_bridge.scratch_page);
+
+ CACHE_FLUSH();
+
+ agp_bridge.tlb_flush(mem);
+
+ return (0);
+}
+
+static agp_memory *intel_i830_alloc_by_type(size_t pg_count,int type)
+{
+ agp_memory *nw;
+
+ /* always return NULL for now */
+ if (type == AGP_DCACHE_MEMORY) return(NULL);
+
+ if (type == AGP_PHYS_MEMORY) {
+ unsigned long physical;
+
+ /* The i830 requires a physical address to program
+ * it's mouse pointer into hardware. However the
+ * Xserver still writes to it through the agp
+ * aperture
+ */
+
+ if (pg_count != 1) return(NULL);
+
+ nw = agp_create_memory(1);
+
+ if (nw == NULL) return(NULL);
+
+ MOD_INC_USE_COUNT;
+ nw->memory[0] = agp_bridge.agp_alloc_page();
+ physical = nw->memory[0];
+ if (nw->memory[0] == 0) {
+ /* free this structure */
+ agp_free_memory(nw);
+ return(NULL);
+ }
+
+ nw->memory[0] = agp_bridge.mask_memory(virt_to_phys((void *) nw->memory[0]),type);
+ nw->page_count = 1;
+ nw->num_scratch_pages = 1;
+ nw->type = AGP_PHYS_MEMORY;
+ nw->physical = virt_to_phys((void *) physical);
+ return(nw);
+ }
+
+ return(NULL);
+}
+
+static int __init intel_i830_setup(struct pci_dev *i830_dev)
+{
+ intel_i830_private.i830_dev = i830_dev;
+
+ agp_bridge.masks = intel_i810_masks;
+ agp_bridge.num_of_masks = 3;
+ agp_bridge.aperture_sizes = (void *) intel_i830_sizes;
+ agp_bridge.size_type = FIXED_APER_SIZE;
+ agp_bridge.num_aperture_sizes = 2;
+
+ agp_bridge.dev_private_data = (void *) &intel_i830_private;
+ agp_bridge.needs_scratch_page = TRUE;
+
+ agp_bridge.configure = intel_i830_configure;
+ agp_bridge.fetch_size = intel_i830_fetch_size;
+ agp_bridge.cleanup = intel_i830_cleanup;
+ agp_bridge.tlb_flush = intel_i810_tlbflush;
+ agp_bridge.mask_memory = intel_i810_mask_memory;
+ agp_bridge.agp_enable = intel_i810_agp_enable;
+ agp_bridge.cache_flush = global_cache_flush;
+
+ agp_bridge.create_gatt_table = intel_i830_create_gatt_table;
+ agp_bridge.free_gatt_table = intel_i830_free_gatt_table;
+
+ agp_bridge.insert_memory = intel_i830_insert_entries;
+ agp_bridge.remove_memory = intel_i830_remove_entries;
+ agp_bridge.alloc_by_type = intel_i830_alloc_by_type;
+ agp_bridge.free_by_type = intel_i810_free_by_type;
+ agp_bridge.agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge.agp_destroy_page = agp_generic_destroy_page;
+
+ agp_bridge.suspend = agp_generic_suspend;
+ agp_bridge.resume = agp_generic_resume;
+ agp_bridge.cant_use_aperture = 0;
+
+ return(0);
+}
+
X #endif /* CONFIG_AGP_I810 */
X
X #ifdef CONFIG_AGP_INTEL
@@ -2976,6 +3260,12 @@
X "Intel",
X "i815",
X intel_generic_setup },
+ { PCI_DEVICE_ID_INTEL_830_M_0,
+ PCI_VENDOR_ID_INTEL,
+ INTEL_I830_M,
+ "Intel",
+ "i830M",
+ intel_generic_setup },
X { PCI_DEVICE_ID_INTEL_840_0,
X PCI_VENDOR_ID_INTEL,
X INTEL_I840,
@@ -3240,17 +3530,38 @@
X PCI_DEVICE_ID_INTEL_815_1,
X NULL);
X if (i810_dev == NULL) {
- printk(KERN_ERR PFX "agpgart: Detected an "
+ printk(KERN_ERR PFX "Detected an "
X "Intel i815, but could not find the"
X " secondary device. Assuming a "
X "non-integrated video card.\n");
X break;
X }
- printk(KERN_INFO PFX "agpgart: Detected an Intel i815 "
+ printk(KERN_INFO PFX "Detected an Intel i815 "
X "Chipset.\n");
X agp_bridge.type = INTEL_I810;
X return intel_i810_setup(i810_dev);
X
+ case PCI_DEVICE_ID_INTEL_830_M_0:
+ i810_dev = pci_find_device(PCI_VENDOR_ID_INTEL,
+ PCI_DEVICE_ID_INTEL_830_M_1,
+ NULL);
+ if(PCI_FUNC(i810_dev->devfn) != 0) {
+ i810_dev = pci_find_device(PCI_VENDOR_ID_INTEL,
+ PCI_DEVICE_ID_INTEL_830_M_1,
+ i810_dev);
+ }
+
+ if (i810_dev == NULL) {
+ printk(KERN_ERR PFX "Detected an "
+ "Intel 830M, but could not find the"
+ " secondary device.\n");
+ agp_bridge.type = NOT_SUPPORTED;
+ return -ENODEV;
+ }
+ printk(KERN_INFO PFX "Detected an Intel "
+ "830M Chipset.\n");
+ agp_bridge.type = INTEL_I810;
+ return intel_i830_setup(i810_dev);
X default:
X break;
X }
diff -u --recursive --new-file v2.4.10/linux/drivers/char/mwave/3780i.c linux/drivers/char/mwave/3780i.c
--- v2.4.10/linux/drivers/char/mwave/3780i.c Wed Dec 31 16:00:00 1969
+++ linux/drivers/char/mwave/3780i.c Sun Sep 30 12:26:05 2001
@@ -0,0 +1,730 @@
+/*
+*
+* 3780i.c -- helper routines for the 3780i DSP
+*
+*
+* Written By: Mike Sullivan IBM Corporation
+*
+* Copyright (C) 1999 IBM Corporation
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; either version 2 of the License, or
+* (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* NO WARRANTY
+* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
+* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
+* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
+* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
+* solely responsible for determining the appropriateness of using and
+* distributing the Program and assumes all risks associated with its
+* exercise of rights under this Agreement, including but not limited to
+* the risks and costs of program errors, damage to or loss of data,
+* programs or equipment, and unavailability or interruption of operations.
+*
+* DISCLAIMER OF LIABILITY
+* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
+* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+*
+*
+* 10/23/2000 - Alpha Release
+* First release to the public
+*/
+
+#include <linux/version.h>
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/unistd.h>
+#include <linux/delay.h>
+#include <linux/ioport.h>
+#include <linux/init.h>
+#include <asm/io.h>
+#include <asm/uaccess.h>
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <asm/bitops.h>
+#include "smapi.h"
+#include "mwavedd.h"
+#include "3780i.h"
+
+static spinlock_t dsp_lock = SPIN_LOCK_UNLOCKED;
+static unsigned long flags;
+
+
+static void PaceMsaAccess(unsigned short usDspBaseIO)
+{
+ if(current->need_resched)
+ schedule();
+ udelay(100);
+ if(current->need_resched)
+ schedule();
+}
+
+unsigned short dsp3780I_ReadMsaCfg(unsigned short usDspBaseIO,
+ unsigned long ulMsaAddr)
+{
+ unsigned short val;
+
+ PRINTK_3(TRACE_3780I,
+ "3780i::dsp3780I_ReadMsaCfg entry usDspBaseIO %x ulMsaAddr %lx\n",
+ usDspBaseIO, ulMsaAddr);
+
+ spin_lock_irqsave(&dsp_lock, flags);
+ OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulMsaAddr);
+ OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulMsaAddr >> 16));
+ val = InWordDsp(DSP_MsaDataDSISHigh);
+ spin_unlock_irqrestore(&dsp_lock, flags);
+
+ PRINTK_2(TRACE_3780I, "3780i::dsp3780I_ReadMsaCfg exit val %x\n", val);
+
+ return val;
+}
+
+void dsp3780I_WriteMsaCfg(unsigned short usDspBaseIO,
+ unsigned long ulMsaAddr, unsigned short usValue)
+{
+
+ PRINTK_4(TRACE_3780I,
+ "3780i::dsp3780i_WriteMsaCfg entry usDspBaseIO %x ulMsaAddr %lx usValue %x\n",
+ usDspBaseIO, ulMsaAddr, usValue);
+
+ spin_lock_irqsave(&dsp_lock, flags);
+ OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulMsaAddr);
+ OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulMsaAddr >> 16));
+ OutWordDsp(DSP_MsaDataDSISHigh, usValue);
+ spin_unlock_irqrestore(&dsp_lock, flags);
+}
+
+void dsp3780I_WriteGenCfg(unsigned short usDspBaseIO, unsigned uIndex,
+ unsigned char ucValue)
+{
+ DSP_ISA_SLAVE_CONTROL rSlaveControl;
+ DSP_ISA_SLAVE_CONTROL rSlaveControl_Save;
+
+
+ PRINTK_4(TRACE_3780I,
+ "3780i::dsp3780i_WriteGenCfg entry usDspBaseIO %x uIndex %x ucValue %x\n",
+ usDspBaseIO, uIndex, ucValue);
+
+ MKBYTE(rSlaveControl) = InByteDsp(DSP_IsaSlaveControl);
+
+ PRINTK_2(TRACE_3780I,
+ "3780i::dsp3780i_WriteGenCfg rSlaveControl %x\n",
+ MKBYTE(rSlaveControl));
+
+ rSlaveControl_Save = rSlaveControl;
+ rSlaveControl.ConfigMode = TRUE;
+
+ PRINTK_2(TRACE_3780I,
+ "3780i::dsp3780i_WriteGenCfg entry rSlaveControl+ConfigMode %x\n",
+ MKBYTE(rSlaveControl));
+
+ OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl));
+ OutByteDsp(DSP_ConfigAddress, (unsigned char) uIndex);
+ OutByteDsp(DSP_ConfigData, ucValue);
+ OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl_Save));
+
+ PRINTK_1(TRACE_3780I, "3780i::dsp3780i_WriteGenCfg exit\n");
+
+
+}
+
+unsigned char dsp3780I_ReadGenCfg(unsigned short usDspBaseIO,
+ unsigned uIndex)
+{
+ DSP_ISA_SLAVE_CONTROL rSlaveControl;
+ DSP_ISA_SLAVE_CONTROL rSlaveControl_Save;
+ unsigned char ucValue;
+
+
+ PRINTK_3(TRACE_3780I,
+ "3780i::dsp3780i_ReadGenCfg entry usDspBaseIO %x uIndex %x\n",
+ usDspBaseIO, uIndex);
+
+ MKBYTE(rSlaveControl) = InByteDsp(DSP_IsaSlaveControl);
+ rSlaveControl_Save = rSlaveControl;
+ rSlaveControl.ConfigMode = TRUE;
+ OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl));
+ OutByteDsp(DSP_ConfigAddress, (unsigned char) uIndex);
+ ucValue = InByteDsp(DSP_ConfigData);
+ OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl_Save));
+
+ PRINTK_2(TRACE_3780I,
+ "3780i::dsp3780i_ReadGenCfg exit ucValue %x\n", ucValue);
+
+
+ return ucValue;
+}
+
+int dsp3780I_EnableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings,
+ unsigned short *pIrqMap,
+ unsigned short *pDmaMap)
+{
+ unsigned short usDspBaseIO = pSettings->usDspBaseIO;
+ int i;
+ DSP_UART_CFG_1 rUartCfg1;
+ DSP_UART_CFG_2 rUartCfg2;
+ DSP_HBRIDGE_CFG_1 rHBridgeCfg1;
+ DSP_HBRIDGE_CFG_2 rHBridgeCfg2;
+ DSP_BUSMASTER_CFG_1 rBusmasterCfg1;
+ DSP_BUSMASTER_CFG_2 rBusmasterCfg2;
+ DSP_ISA_PROT_CFG rIsaProtCfg;
+ DSP_POWER_MGMT_CFG rPowerMgmtCfg;
+ DSP_HBUS_TIMER_CFG rHBusTimerCfg;
+ DSP_LBUS_TIMEOUT_DISABLE rLBusTimeoutDisable;
+ DSP_CHIP_RESET rChipReset;
+ DSP_CLOCK_CONTROL_1 rClockControl1;
+ DSP_CLOCK_CONTROL_2 rClockControl2;
+ DSP_ISA_SLAVE_CONTROL rSlaveControl;
+ DSP_HBRIDGE_CONTROL rHBridgeControl;
+ unsigned short ChipID = 0;
+ unsigned short tval;
+
+
+ PRINTK_2(TRACE_3780I,
+ "3780i::dsp3780I_EnableDSP entry pSettings->bDSPEnabled %x\n",
+ pSettings->bDSPEnabled);
+
+
+ if (!pSettings->bDSPEnabled) {
+ PRINTK_ERROR( KERN_ERR "3780i::dsp3780I_EnableDSP: Error: DSP not enabled. Aborting.\n" );
+ return -EIO;
+ }
+
+
+ PRINTK_2(TRACE_3780I,
+ "3780i::dsp3780i_EnableDSP entry pSettings->bModemEnabled %x\n",
+ pSettings->bModemEnabled);
+
+ if (pSettings->bModemEnabled) {
+ rUartCfg1.Reserved = rUartCfg2.Reserved = 0;
+ rUartCfg1.IrqActiveLow = pSettings->bUartIrqActiveLow;
+ rUartCfg1.IrqPulse = pSettings->bUartIrqPulse;
+ rUartCfg1.Irq =
+ (unsigned char) pIrqMap[pSettings->usUartIrq];
+ switch (pSettings->usUartBaseIO) {
+ case 0x03F8:
+ rUartCfg1.BaseIO = 0;
+ break;
+ case 0x02F8:
+ rUartCfg1.BaseIO = 1;
+ break;
+ case 0x03E8:
+ rUartCfg1.BaseIO = 2;
+ break;
+ case 0x02E8:
+ rUartCfg1.BaseIO = 3;
+ break;
+ }
+ rUartCfg2.Enable = TRUE;
+ }
+
+ rHBridgeCfg1.Reserved = rHBridgeCfg2.Reserved = 0;
+ rHBridgeCfg1.IrqActiveLow = pSettings->bDspIrqActiveLow;
+ rHBridgeCfg1.IrqPulse = pSettings->bDspIrqPulse;
+ rHBridgeCfg1.Irq = (unsigned char) pIrqMap[pSettings->usDspIrq];
+ rHBridgeCfg1.AccessMode = 1;
+ rHBridgeCfg2.Enable = TRUE;
+
+
+ rBusmasterCfg2.Reserved = 0;
+ rBusmasterCfg1.Dma = (unsigned char) pDmaMap[pSettings->usDspDma];
+ rBusmasterCfg1.NumTransfers =
+ (unsigned char) pSettings->usNumTransfers;
+ rBusmasterCfg1.ReRequest = (unsigned char) pSettings->usReRequest;
+ rBusmasterCfg1.MEMCS16 = pSettings->bEnableMEMCS16;
+ rBusmasterCfg2.IsaMemCmdWidth =
+ (unsigned char) pSettings->usIsaMemCmdWidth;
+
+
+ rIsaProtCfg.Reserved = 0;
+ rIsaProtCfg.GateIOCHRDY = pSettings->bGateIOCHRDY;
+
+ rPowerMgmtCfg.Reserved = 0;
+ rPowerMgmtCfg.Enable = pSettings->bEnablePwrMgmt;
+
+ rHBusTimerCfg.LoadValue =
+ (unsigned char) pSettings->usHBusTimerLoadValue;
+
+ rLBusTimeoutDisable.Reserved = 0;
+ rLBusTimeoutDisable.DisableTimeout =
+ pSettings->bDisableLBusTimeout;
+
+ MKWORD(rChipReset) = ~pSettings->usChipletEnable;
+
+ rClockControl1.Reserved1 = rClockControl1.Reserved2 = 0;
+ rClockControl1.N_Divisor = pSettings->usN_Divisor;
+ rClockControl1.M_Multiplier = pSettings->usM_Multiplier;
+
+ rClockControl2.Reserved = 0;
+ rClockControl2.PllBypass = pSettings->bPllBypass;
+
+ /* Issue a soft reset to the chip */
+ /* Note: Since we may be coming in with 3780i clocks suspended, we must keep
+ * soft-reset active for 10ms.
+ */
+ rSlaveControl.ClockControl = 0;
+ rSlaveControl.SoftReset = TRUE;
+ rSlaveControl.ConfigMode = FALSE;
+ rSlaveControl.Reserved = 0;
+
+ PRINTK_4(TRACE_3780I,
+ "3780i::dsp3780i_EnableDSP usDspBaseIO %x index %x taddr %x\n",
+ usDspBaseIO, DSP_IsaSlaveControl,
+ usDspBaseIO + DSP_IsaSlaveControl);
+
+ PRINTK_2(TRACE_3780I,
+ "3780i::dsp3780i_EnableDSP rSlaveContrl %x\n",
+ MKWORD(rSlaveControl));
+
+ spin_lock_irqsave(&dsp_lock, flags);
+ OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl));
+ MKWORD(tval) = InWordDsp(DSP_IsaSlaveControl);
+
+ PRINTK_2(TRACE_3780I,
+ "3780i::dsp3780i_EnableDSP rSlaveControl 2 %x\n", tval);
+
+
+ for (i = 0; i < 11; i++)
+ udelay(2000);
+
+ rSlaveControl.SoftReset = FALSE;
+ OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl));
+
+ MKWORD(tval) = InWordDsp(DSP_IsaSlaveControl);
+
+ PRINTK_2(TRACE_3780I,
+ "3780i::dsp3780i_EnableDSP rSlaveControl 3 %x\n", tval);
+
+
+ /* Program our general configuration registers */
+ WriteGenCfg(DSP_HBridgeCfg1Index, MKBYTE(rHBridgeCfg1));
+ WriteGenCfg(DSP_HBridgeCfg2Index, MKBYTE(rHBridgeCfg2));
+ WriteGenCfg(DSP_BusMasterCfg1Index, MKBYTE(rBusmasterCfg1));
+ WriteGenCfg(DSP_BusMasterCfg2Index, MKBYTE(rBusmasterCfg2));
+ WriteGenCfg(DSP_IsaProtCfgIndex, MKBYTE(rIsaProtCfg));
+ WriteGenCfg(DSP_PowerMgCfgIndex, MKBYTE(rPowerMgmtCfg));
+ WriteGenCfg(DSP_HBusTimerCfgIndex, MKBYTE(rHBusTimerCfg));
+
+ if (pSettings->bModemEnabled) {
+ WriteGenCfg(DSP_UartCfg1Index, MKBYTE(rUartCfg1));
+ WriteGenCfg(DSP_UartCfg2Index, MKBYTE(rUartCfg2));
+ }
+
+
+ rHBridgeControl.EnableDspInt = FALSE;
+ rHBridgeControl.MemAutoInc = TRUE;
+ rHBridgeControl.IoAutoInc = FALSE;
+ rHBridgeControl.DiagnosticMode = FALSE;
+
+ PRINTK_3(TRACE_3780I,
+ "3780i::dsp3780i_EnableDSP DSP_HBridgeControl %x rHBridgeControl %x\n",
+ DSP_HBridgeControl, MKWORD(rHBridgeControl));
+
+ OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));
+ spin_unlock_irqrestore(&dsp_lock, flags);
+ WriteMsaCfg(DSP_LBusTimeoutDisable, MKWORD(rLBusTimeoutDisable));
+ WriteMsaCfg(DSP_ClockControl_1, MKWORD(rClockControl1));
+ WriteMsaCfg(DSP_ClockControl_2, MKWORD(rClockControl2));
+ WriteMsaCfg(DSP_ChipReset, MKWORD(rChipReset));
+
+ ChipID = ReadMsaCfg(DSP_ChipID);
+
+ PRINTK_2(TRACE_3780I,
+ "3780i::dsp3780I_EnableDSP exiting bRC=TRUE, ChipID %x\n",
+ ChipID);
+
+ return 0;
+}
+
+int dsp3780I_DisableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings)
+{
+ unsigned short usDspBaseIO = pSettings->usDspBaseIO;
+ DSP_ISA_SLAVE_CONTROL rSlaveControl;
+
+
+ PRINTK_1(TRACE_3780I, "3780i::dsp3780i_DisableDSP entry\n");
+
+ rSlaveControl.ClockControl = 0;
+ rSlaveControl.SoftReset = TRUE;
+ rSlaveControl.ConfigMode = FALSE;
+ rSlaveControl.Reserved = 0;
+ spin_lock_irqsave(&dsp_lock, flags);
+ OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl));
+
+ udelay(5);
+
+ rSlaveControl.ClockControl = 1;
+ OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl));
+ spin_unlock_irqrestore(&dsp_lock, flags);
+
+ udelay(5);
+
+
+ PRINTK_1(TRACE_3780I, "3780i::dsp3780i_DisableDSP exit\n");
+
+ return 0;
+}
+
+int dsp3780I_Reset(DSP_3780I_CONFIG_SETTINGS * pSettings)
+{
+ unsigned short usDspBaseIO = pSettings->usDspBaseIO;
+ DSP_BOOT_DOMAIN rBootDomain;
+ DSP_HBRIDGE_CONTROL rHBridgeControl;
+
+
+ PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Reset entry\n");
+
+ spin_lock_irqsave(&dsp_lock, flags);
+ /* Mask DSP to PC interrupt */
+ MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl);
+
+ PRINTK_2(TRACE_3780I, "3780i::dsp3780i_Reset rHBridgeControl %x\n",
+ MKWORD(rHBridgeControl));
+
+ rHBridgeControl.EnableDspInt = FALSE;
+ OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));
+ spin_unlock_irqrestore(&dsp_lock, flags);
+
+ /* Reset the core via the boot domain register */
+ rBootDomain.ResetCore = TRUE;
+ rBootDomain.Halt = TRUE;
+ rBootDomain.NMI = TRUE;
+ rBootDomain.Reserved = 0;
+
+ PRINTK_2(TRACE_3780I, "3780i::dsp3780i_Reset rBootDomain %x\n",
+ MKWORD(rBootDomain));
+
+ WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain));
+
+ /* Reset all the chiplets and then reactivate them */
+ WriteMsaCfg(DSP_ChipReset, 0xFFFF);
+ udelay(5);
+ WriteMsaCfg(DSP_ChipReset,
+ (unsigned short) (~pSettings->usChipletEnable));
+
+
+ PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Reset exit bRC=0\n");
+
+ return 0;
+}
+
+
+int dsp3780I_Run(DSP_3780I_CONFIG_SETTINGS * pSettings)
+{
+ unsigned short usDspBaseIO = pSettings->usDspBaseIO;
+ DSP_BOOT_DOMAIN rBootDomain;
+ DSP_HBRIDGE_CONTROL rHBridgeControl;
+
+
+ PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Run entry\n");
+
+
+ /* Transition the core to a running state */
+ rBootDomain.ResetCore = TRUE;
+ rBootDomain.Halt = FALSE;
+ rBootDomain.NMI = TRUE;
+ rBootDomain.Reserved = 0;
+ WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain));
+
+ udelay(5);
+
+ rBootDomain.ResetCore = FALSE;
+ WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain));
+ udelay(5);
+
+ rBootDomain.NMI = FALSE;
+ WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain));
+ udelay(5);
+
+ /* Enable DSP to PC interrupt */
+ spin_lock_irqsave(&dsp_lock, flags);
+ MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl);
+ rHBridgeControl.EnableDspInt = TRUE;
+
+ PRINTK_2(TRACE_3780I, "3780i::dsp3780i_Run rHBridgeControl %x\n",
+ MKWORD(rHBridgeControl));
+
+ OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));
+ spin_unlock_irqrestore(&dsp_lock, flags);
+
+
+ PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Run exit bRC=TRUE\n");
+
+ return 0;
+}
+
+
+int dsp3780I_ReadDStore(unsigned short usDspBaseIO, void *pvBuffer,
+ unsigned uCount, unsigned long ulDSPAddr)
+{
+ unsigned short *pusBuffer = pvBuffer;
+ unsigned short val;
+
+
+ PRINTK_5(TRACE_3780I,
+ "3780i::dsp3780I_ReadDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
+ usDspBaseIO, pusBuffer, uCount, ulDSPAddr);
+
+
+ /* Set the initial MSA address. No adjustments need to be made to data store addresses */
+ spin_lock_irqsave(&dsp_lock, flags);
+ OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);
+ OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));
+ spin_unlock_irqrestore(&dsp_lock, flags);
+
+ /* Transfer the memory block */
+ while (uCount-- != 0) {
+ spin_lock_irqsave(&dsp_lock, flags);
+ val = InWordDsp(DSP_MsaDataDSISHigh);
+ spin_unlock_irqrestore(&dsp_lock, flags);
+ if(put_user(val, pusBuffer++))
+ return -EFAULT;
+
+ PRINTK_3(TRACE_3780I,
+ "3780I::dsp3780I_ReadDStore uCount %x val %x\n",
+ uCount, val);
+
+ PaceMsaAccess(usDspBaseIO);
+ }
+
+
+ PRINTK_1(TRACE_3780I,
+ "3780I::dsp3780I_ReadDStore exit bRC=TRUE\n");
+
+ return 0;
+}
+
+int dsp3780I_ReadAndClearDStore(unsigned short usDspBaseIO,
+ void *pvBuffer, unsigned uCount,
+ unsigned long ulDSPAddr)
+{
+ unsigned short *pusBuffer = pvBuffer;
+ unsigned short val;
+
+
+ PRINTK_5(TRACE_3780I,
+ "3780i::dsp3780I_ReadAndDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
+ usDspBaseIO, pusBuffer, uCount, ulDSPAddr);
+
+
+ /* Set the initial MSA address. No adjustments need to be made to data store addresses */
+ spin_lock_irqsave(&dsp_lock, flags);
+ OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);
+ OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));
+ spin_unlock_irqrestore(&dsp_lock, flags);
+
+ /* Transfer the memory block */
+ while (uCount-- != 0) {
+ spin_lock_irqsave(&dsp_lock, flags);
+ val = InWordDsp(DSP_ReadAndClear);
+ spin_unlock_irqrestore(&dsp_lock, flags);
+ if(put_user(val, pusBuffer++))
+ return -EFAULT;
+
+ PRINTK_3(TRACE_3780I,
+ "3780I::dsp3780I_ReadAndCleanDStore uCount %x val %x\n",
+ uCount, val);
+
+ PaceMsaAccess(usDspBaseIO);
+ }
+
+
+ PRINTK_1(TRACE_3780I,
+ "3780I::dsp3780I_ReadAndClearDStore exit bRC=TRUE\n");
+
+ return 0;
+}
+
+
+int dsp3780I_WriteDStore(unsigned short usDspBaseIO, void *pvBuffer,
+ unsigned uCount, unsigned long ulDSPAddr)
+{
+ unsigned short *pusBuffer = pvBuffer;
+
+
+ PRINTK_5(TRACE_3780I,
+ "3780i::dsp3780D_WriteDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
+ usDspBaseIO, pusBuffer, uCount, ulDSPAddr);
+
+
+ /* Set the initial MSA address. No adjustments need to be made to data store addresses */
+ spin_lock_irqsave(&dsp_lock, flags);
+ OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);
+ OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));
+ spin_unlock_irqrestore(&dsp_lock, flags);
+
+ /* Transfer the memory block */
+ while (uCount-- != 0) {
+ unsigned short val;
+ if(get_user(val, pusBuffer++))
+ return -EFAULT;
+ spin_lock_irqsave(&dsp_lock, flags);
+ OutWordDsp(DSP_MsaDataDSISHigh, val);
+ spin_unlock_irqrestore(&dsp_lock, flags);
+
+ PRINTK_3(TRACE_3780I,
+ "3780I::dsp3780I_WriteDStore uCount %x val %x\n",
+ uCount, val);
+
+ PaceMsaAccess(usDspBaseIO);
+ }
+
+
+ PRINTK_1(TRACE_3780I,
+ "3780I::dsp3780D_WriteDStore exit bRC=TRUE\n");
+
+ return 0;
+}
+
+
+int dsp3780I_ReadIStore(unsigned short usDspBaseIO, void *pvBuffer,
+ unsigned uCount, unsigned long ulDSPAddr)
+{
+ unsigned short *pusBuffer = pvBuffer;
+
+ PRINTK_5(TRACE_3780I,
+ "3780i::dsp3780I_ReadIStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
+ usDspBaseIO, pusBuffer, uCount, ulDSPAddr);
+
+ /*
+ * Set the initial MSA address. To convert from an instruction store
+ * address to an MSA address
+ * shift the address two bits to the left and set bit 22
+ */
+ ulDSPAddr = (ulDSPAddr << 2) | (1 << 22);
+ spin_lock_irqsave(&dsp_lock, flags);
+ OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);
+ OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));
+ spin_unlock_irqrestore(&dsp_lock, flags);
+
+ /* Transfer the memory block */
+ while (uCount-- != 0) {
+ unsigned short val_lo, val_hi;
+ spin_lock_irqsave(&dsp_lock, flags);
+ val_lo = InWordDsp(DSP_MsaDataISLow);
+ val_hi = InWordDsp(DSP_MsaDataDSISHigh);
+ spin_unlock_irqrestore(&dsp_lock, flags);
+ if(put_user(val_lo, pusBuffer++))
+ return -EFAULT;
+ if(put_user(val_hi, pusBuffer++))
+ return -EFAULT;
+
+ PRINTK_4(TRACE_3780I,
+ "3780I::dsp3780I_ReadIStore uCount %x val_lo %x val_hi %x\n",
+ uCount, val_lo, val_hi);
+
+ PaceMsaAccess(usDspBaseIO);
+
+ }
+
+ PRINTK_1(TRACE_3780I,
+ "3780I::dsp3780I_ReadIStore exit bRC=TRUE\n");
+
+ return 0;
+}
+
+
+int dsp3780I_WriteIStore(unsigned short usDspBaseIO, void *pvBuffer,
+ unsigned uCount, unsigned long ulDSPAddr)
+{
+ unsigned short *pusBuffer = pvBuffer;
+
+ PRINTK_5(TRACE_3780I,
+ "3780i::dsp3780I_WriteIStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
+ usDspBaseIO, pusBuffer, uCount, ulDSPAddr);
+
+
+ /*
+ * Set the initial MSA address. To convert from an instruction store
+ * address to an MSA address
+ * shift the address two bits to the left and set bit 22
+ */
+ ulDSPAddr = (ulDSPAddr << 2) | (1 << 22);
+ spin_lock_irqsave(&dsp_lock, flags);
+ OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);
+ OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));
+ spin_unlock_irqrestore(&dsp_lock, flags);
+
+ /* Transfer the memory block */
+ while (uCount-- != 0) {
+ unsigned short val_lo, val_hi;
+ if(get_user(val_lo, pusBuffer++))
+ return -EFAULT;
+ if(get_user(val_hi, pusBuffer++))
+ return -EFAULT;
+ spin_lock_irqsave(&dsp_lock, flags);
+ OutWordDsp(DSP_MsaDataISLow, val_lo);
+ OutWordDsp(DSP_MsaDataDSISHigh, val_hi);
+ spin_unlock_irqrestore(&dsp_lock, flags);
+
+ PRINTK_4(TRACE_3780I,
+ "3780I::dsp3780I_WriteIStore uCount %x val_lo %x val_hi %x\n",
+ uCount, val_lo, val_hi);
+
+ PaceMsaAccess(usDspBaseIO);
+
+ }
+
+ PRINTK_1(TRACE_3780I,
+ "3780I::dsp3780I_WriteIStore exit bRC=TRUE\n");
+
+ return 0;
+}
+
+
+int dsp3780I_GetIPCSource(unsigned short usDspBaseIO,
+ unsigned short *pusIPCSource)
+{
+ DSP_HBRIDGE_CONTROL rHBridgeControl;
+ unsigned short temp;
+
+
+ PRINTK_3(TRACE_3780I,
+ "3780i::dsp3780I_GetIPCSource entry usDspBaseIO %x pusIPCSource %p\n",
+ usDspBaseIO, pusIPCSource);
+
+ /*
+ * Disable DSP to PC interrupts, read the interupt register,
+ * clear the pending IPC bits, and reenable DSP to PC interrupts
+ */
+ spin_lock_irqsave(&dsp_lock, flags);
+ MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl);
+ rHBridgeControl.EnableDspInt = FALSE;
+ OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));
+
+ *pusIPCSource = InWordDsp(DSP_Interrupt);
+ temp = (unsigned short) ~(*pusIPCSource);
+
+ PRINTK_3(TRACE_3780I,
+ "3780i::dsp3780I_GetIPCSource, usIPCSource %x ~ %x\n",
+ *pusIPCSource, temp);
+
+ OutWordDsp(DSP_Interrupt, (unsigned short) ~(*pusIPCSource));
+
+ rHBridgeControl.EnableDspInt = TRUE;
+ OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));
+ spin_unlock_irqrestore(&dsp_lock, flags);
+
+
+ PRINTK_2(TRACE_3780I,
+ "3780i::dsp3780I_GetIPCSource exit usIPCSource %x\n",
+ *pusIPCSource);
+
+ return 0;
+}
diff -u --recursive --new-file v2.4.10/linux/drivers/char/mwave/3780i.h linux/drivers/char/mwave/3780i.h
--- v2.4.10/linux/drivers/char/mwave/3780i.h Wed Dec 31 16:00:00 1969
+++ linux/drivers/char/mwave/3780i.h Sun Sep 30 12:26:05 2001
@@ -0,0 +1,362 @@
+/*
+*
+* 3780i.h -- declarations for 3780i.c
+*
+*
+* Written By: Mike Sullivan IBM Corporation
+*
+* Copyright (C) 1999 IBM Corporation
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; either version 2 of the License, or
+* (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* NO WARRANTY
+* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
+* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
+* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
+* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
+* solely responsible for determining the appropriateness of using and
+* distributing the Program and assumes all risks associated with its
+* exercise of rights under this Agreement, including but not limited to
+* the risks and costs of program errors, damage to or loss of data,
+* programs or equipment, and unavailability or interruption of operations.
+*
+* DISCLAIMER OF LIABILITY
+* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
+* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+*
+*
+* 10/23/2000 - Alpha Release
+* First release to the public
+*/
+
+#ifndef _LINUX_3780I_H
+#define _LINUX_3780I_H
+
+#include <asm/io.h>
+
+/* DSP I/O port offsets and definitions */
+#define DSP_IsaSlaveControl 0x0000 /* ISA slave control register */
+#define DSP_IsaSlaveStatus 0x0001 /* ISA slave status register */
+#define DSP_ConfigAddress 0x0002 /* General config address register */
+#define DSP_ConfigData 0x0003 /* General config data register */
+#define DSP_HBridgeControl 0x0002 /* HBridge control register */
+#define DSP_MsaAddrLow 0x0004 /* MSP System Address, low word */
+#define DSP_MsaAddrHigh 0x0006 /* MSP System Address, high word */
+#define DSP_MsaDataDSISHigh 0x0008 /* MSA data register: d-store word or high byte of i-store */
+#define DSP_MsaDataISLow 0x000A /* MSA data register: low word of i-store */
+#define DSP_ReadAndClear 0x000C /* MSA read and clear data register */
+#define DSP_Interrupt 0x000E /* Interrupt register (IPC source) */
+
+typedef struct {
+ unsigned char ClockControl:1; /* RW: Clock control: 0=normal, 1=stop 3780i clocks */
+ unsigned char SoftReset:1; /* RW: Soft reset 0=normal, 1=soft reset active */
+ unsigned char ConfigMode:1; /* RW: Configuration mode, 0=normal, 1=config mode */
+ unsigned char Reserved:5; /* 0: Reserved */
+} DSP_ISA_SLAVE_CONTROL;
+
+
+typedef struct {
+ unsigned short EnableDspInt:1; /* RW: Enable DSP to X86 ISA interrupt 0=mask it, 1=enable it */
+ unsigned short MemAutoInc:1; /* RW: Memory address auto increment, 0=disable, 1=enable */
+ unsigned short IoAutoInc:1; /* RW: I/O address auto increment, 0=disable, 1=enable */
+ unsigned short DiagnosticMode:1; /* RW: Disgnostic mode 0=nromal, 1=diagnostic mode */
+ unsigned short IsaPacingTimer:12; /* R: ISA access pacing timer: count of core cycles stolen */
+} DSP_HBRIDGE_CONTROL;
+
+
+/* DSP register indexes used with the configuration register address (index) register */
+#define DSP_UartCfg1Index 0x0003 /* UART config register 1 */
+#define DSP_UartCfg2Index 0x0004 /* UART config register 2 */
+#define DSP_HBridgeCfg1Index 0x0007 /* HBridge config register 1 */
+#define DSP_HBridgeCfg2Index 0x0008 /* HBridge config register 2 */
+#define DSP_BusMasterCfg1Index 0x0009 /* ISA bus master config register 1 */
+#define DSP_BusMasterCfg2Index 0x000A /* ISA bus master config register 2 */
+#define DSP_IsaProtCfgIndex 0x000F /* ISA protocol control register */
+#define DSP_PowerMgCfgIndex 0x0010 /* Low poser suspend/resume enable */
+#define DSP_HBusTimerCfgIndex 0x0011 /* HBUS timer load value */
+
+typedef struct {
+ unsigned char IrqActiveLow:1; /* RW: IRQ active high or low: 0=high, 1=low */
+ unsigned char IrqPulse:1; /* RW: IRQ pulse or level: 0=level, 1=pulse */
+ unsigned char Irq:3; /* RW: IRQ selection */
+ unsigned char BaseIO:2; /* RW: Base I/O selection */
+ unsigned char Reserved:1; /* 0: Reserved */
+} DSP_UART_CFG_1;
+
+typedef struct {
+ unsigned char Enable:1; /* RW: Enable I/O and IRQ: 0=FALSE, 1=TRUE */
SHAR_EOF
true || echo 'restore of patch-2.4.11 failed'
fi
echo 'End of part 06'
echo 'File patch-2.4.11 is continued in part 07'
echo "07" > _shar_seq_.tmp
exit 0
Thomas Kobienia
#!/bin/sh -x
# this is part 07 of a 77 - part archive
# do not concatenate these parts, unpack them in order with /bin/sh
# file patch-2.4.11 continued
if test ! -r _shar_seq_.tmp; then
echo 'Please unpack part 1 first!'
exit 1
fi
(read Scheck
if test "$Scheck" != 07; then
echo "Please unpack part $Scheck next!"
exit 1
else
exit 0
fi
) < _shar_seq_.tmp || exit 1
if test ! -f _shar_wnt_.tmp; then
echo 'x - still skipping patch-2.4.11'
else
echo 'x - continuing with patch-2.4.11'
sed 's/^X//' << 'SHAR_EOF' >> 'patch-2.4.11' &&
+ unsigned char Reserved:7; /* 0: Reserved */
+} DSP_UART_CFG_2;
+
+typedef struct {
+ unsigned char IrqActiveLow:1; /* RW: IRQ active high=0 or low=1 */
+ unsigned char IrqPulse:1; /* RW: IRQ pulse=1 or level=0 */
+ unsigned char Irq:3; /* RW: IRQ selection */
+ unsigned char AccessMode:1; /* RW: 16-bit register access method 0=byte, 1=word */
+ unsigned char Reserved:2; /* 0: Reserved */
+} DSP_HBRIDGE_CFG_1;
+
+typedef struct {
+ unsigned char Enable:1; /* RW: enable I/O and IRQ: 0=FALSE, 1=TRUE */
+ unsigned char Reserved:7; /* 0: Reserved */
+} DSP_HBRIDGE_CFG_2;
+
+
+typedef struct {
+ unsigned char Dma:3; /* RW: DMA channel selection */
+ unsigned char NumTransfers:2; /* RW: Maximum # of transfers once being granted the ISA bus */
+ unsigned char ReRequest:2; /* RW: Minumum delay between releasing the ISA bus and requesting it again */
+ unsigned char MEMCS16:1; /* RW: ISA signal MEMCS16: 0=disabled, 1=enabled */
+} DSP_BUSMASTER_CFG_1;
+
+typedef struct {
+ unsigned char IsaMemCmdWidth:2; /* RW: ISA memory command width */
+ unsigned char Reserved:6; /* 0: Reserved */
+} DSP_BUSMASTER_CFG_2;
+
+
+typedef struct {
+ unsigned char GateIOCHRDY:1; /* RW: Enable IOCHRDY gating: 0=FALSE, 1=TRUE */
+ unsigned char Reserved:7; /* 0: Reserved */
+} DSP_ISA_PROT_CFG;
+
+typedef struct {
+ unsigned char Enable:1; /* RW: Enable low power suspend/resume 0=FALSE, 1=TRUE */
+ unsigned char Reserved:7; /* 0: Reserved */
+} DSP_POWER_MGMT_CFG;
+
+typedef struct {
+ unsigned char LoadValue:8; /* RW: HBUS timer load value */
+} DSP_HBUS_TIMER_CFG;
+
+
+
+/* DSP registers that exist in MSA I/O space */
+#define DSP_ChipID 0x80000000
+#define DSP_MspBootDomain 0x80000580
+#define DSP_LBusTimeoutDisable 0x80000580
+#define DSP_ClockControl_1 0x8000058A
+#define DSP_ClockControl_2 0x8000058C
+#define DSP_ChipReset 0x80000588
+#define DSP_GpioModeControl_15_8 0x80000082
+#define DSP_GpioDriverEnable_15_8 0x80000076
+#define DSP_GpioOutputData_15_8 0x80000072
+
+typedef struct {
+ unsigned short NMI:1; /* RW: non maskable interrupt */
+ unsigned short Halt:1; /* RW: Halt MSP clock */
+ unsigned short ResetCore:1; /* RW: Reset MSP core interface */
+ unsigned short Reserved:13; /* 0: Reserved */
+} DSP_BOOT_DOMAIN;
+
+typedef struct {
+ unsigned short DisableTimeout:1; /* RW: Disable LBus timeout */
+ unsigned short Reserved:15; /* 0: Reserved */
+} DSP_LBUS_TIMEOUT_DISABLE;
+
+typedef struct {
+ unsigned short Memory:1; /* RW: Reset memory interface */
+ unsigned short SerialPort1:1; /* RW: Reset serial port 1 interface */
+ unsigned short SerialPort2:1; /* RW: Reset serial port 2 interface */
+ unsigned short SerialPort3:1; /* RW: Reset serial port 3 interface */
+ unsigned short Gpio:1; /* RW: Reset GPIO interface */
+ unsigned short Dma:1; /* RW: Reset DMA interface */
+ unsigned short SoundBlaster:1; /* RW: Reset soundblaster interface */
+ unsigned short Uart:1; /* RW: Reset UART interface */
+ unsigned short Midi:1; /* RW: Reset MIDI interface */
+ unsigned short IsaMaster:1; /* RW: Reset ISA master interface */
+ unsigned short Reserved:6; /* 0: Reserved */
+} DSP_CHIP_RESET;
+
+typedef struct {
+ unsigned short N_Divisor:6; /* RW: (N) PLL output clock divisor */
+ unsigned short Reserved1:2; /* 0: reserved */
+ unsigned short M_Multiplier:6; /* RW: (M) PLL feedback clock multiplier */
+ unsigned short Reserved2:2; /* 0: reserved */
+} DSP_CLOCK_CONTROL_1;
+
+typedef struct {
+ unsigned short PllBypass:1; /* RW: PLL Bypass */
+ unsigned short Reserved:15; /* 0: Reserved */
+} DSP_CLOCK_CONTROL_2;
+
+typedef struct {
+ unsigned short Latch8:1;
+ unsigned short Latch9:1;
+ unsigned short Latch10:1;
+ unsigned short Latch11:1;
+ unsigned short Latch12:1;
+ unsigned short Latch13:1;
+ unsigned short Latch14:1;
+ unsigned short Latch15:1;
+ unsigned short Mask8:1;
+ unsigned short Mask9:1;
+ unsigned short Mask10:1;
+ unsigned short Mask11:1;
+ unsigned short Mask12:1;
+ unsigned short Mask13:1;
+ unsigned short Mask14:1;
+ unsigned short Mask15:1;
+} DSP_GPIO_OUTPUT_DATA_15_8;
+
+typedef struct {
+ unsigned short Enable8:1;
+ unsigned short Enable9:1;
+ unsigned short Enable10:1;
+ unsigned short Enable11:1;
+ unsigned short Enable12:1;
+ unsigned short Enable13:1;
+ unsigned short Enable14:1;
+ unsigned short Enable15:1;
+ unsigned short Mask8:1;
+ unsigned short Mask9:1;
+ unsigned short Mask10:1;
+ unsigned short Mask11:1;
+ unsigned short Mask12:1;
+ unsigned short Mask13:1;
+ unsigned short Mask14:1;
+ unsigned short Mask15:1;
+} DSP_GPIO_DRIVER_ENABLE_15_8;
+
+typedef struct {
+ unsigned short GpioMode8:2;
+ unsigned short GpioMode9:2;
+ unsigned short GpioMode10:2;
+ unsigned short GpioMode11:2;
+ unsigned short GpioMode12:2;
+ unsigned short GpioMode13:2;
+ unsigned short GpioMode14:2;
+ unsigned short GpioMode15:2;
+} DSP_GPIO_MODE_15_8;
+
+/* Component masks that are defined in dspmgr.h */
+#define MW_ADC_MASK 0x0001
+#define MW_AIC2_MASK 0x0006
+#define MW_MIDI_MASK 0x0008
+#define MW_CDDAC_MASK 0x8001
+#define MW_AIC1_MASK 0xE006
+#define MW_UART_MASK 0xE00A
+#define MW_ACI_MASK 0xE00B
+
+/*
+* Definition of 3780i configuration structure. Unless otherwise stated,
+* these values are provided as input to the 3780i support layer. At present,
+* the only values maintained by the 3780i support layer are the saved UART
+* registers.
+*/
+typedef struct _DSP_3780I_CONFIG_SETTINGS {
+
+ /* Location of base configuration register */
+ unsigned short usBaseConfigIO;
+
+ /* Enables for various DSP components */
+ int bDSPEnabled;
+ int bModemEnabled;
+ int bInterruptClaimed;
+
+ /* IRQ, DMA, and Base I/O addresses for various DSP components */
+ unsigned short usDspIrq;
+ unsigned short usDspDma;
+ unsigned short usDspBaseIO;
+ unsigned short usUartIrq;
+ unsigned short usUartBaseIO;
+
+ /* IRQ modes for various DSP components */
+ int bDspIrqActiveLow;
+ int bUartIrqActiveLow;
+ int bDspIrqPulse;
+ int bUartIrqPulse;
+
+ /* Card abilities */
+ unsigned uIps;
+ unsigned uDStoreSize;
+ unsigned uIStoreSize;
+ unsigned uDmaBandwidth;
+
+ /* Adapter specific 3780i settings */
+ unsigned short usNumTransfers;
+ unsigned short usReRequest;
+ int bEnableMEMCS16;
+ unsigned short usIsaMemCmdWidth;
+ int bGateIOCHRDY;
+ int bEnablePwrMgmt;
+ unsigned short usHBusTimerLoadValue;
+ int bDisableLBusTimeout;
+ unsigned short usN_Divisor;
+ unsigned short usM_Multiplier;
+ int bPllBypass;
+ unsigned short usChipletEnable; /* Used with the chip reset register to enable specific chiplets */
+
+ /* Saved UART registers. These are maintained by the 3780i support layer. */
+ int bUartSaved; /* True after a successful save of the UART registers */
+ unsigned char ucIER; /* Interrupt enable register */
+ unsigned char ucFCR; /* FIFO control register */
+ unsigned char ucLCR; /* Line control register */
+ unsigned char ucMCR; /* Modem control register */
+ unsigned char ucSCR; /* Scratch register */
+ unsigned char ucDLL; /* Divisor latch, low byte */
+ unsigned char ucDLM; /* Divisor latch, high byte */
+} DSP_3780I_CONFIG_SETTINGS;
+
+
+/* 3780i support functions */
+int dsp3780I_EnableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings,
+ unsigned short *pIrqMap,
+ unsigned short *pDmaMap);
+int dsp3780I_DisableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings);
+int dsp3780I_Reset(DSP_3780I_CONFIG_SETTINGS * pSettings);
+int dsp3780I_Run(DSP_3780I_CONFIG_SETTINGS * pSettings);
+int dsp3780I_ReadDStore(unsigned short usDspBaseIO, void *pvBuffer,
+ unsigned uCount, unsigned long ulDSPAddr);
+int dsp3780I_ReadAndClearDStore(unsigned short usDspBaseIO,
+ void *pvBuffer, unsigned uCount,
+ unsigned long ulDSPAddr);
+int dsp3780I_WriteDStore(unsigned short usDspBaseIO, void *pvBuffer,
+ unsigned uCount, unsigned long ulDSPAddr);
+int dsp3780I_ReadIStore(unsigned short usDspBaseIO, void *pvBuffer,
+ unsigned uCount, unsigned long ulDSPAddr);
+int dsp3780I_WriteIStore(unsigned short usDspBaseIO, void *pvBuffer,
+ unsigned uCount, unsigned long ulDSPAddr);
+unsigned short dsp3780I_ReadMsaCfg(unsigned short usDspBaseIO,
+ unsigned long ulMsaAddr);
+void dsp3780I_WriteMsaCfg(unsigned short usDspBaseIO,
+ unsigned long ulMsaAddr, unsigned short usValue);
+void dsp3780I_WriteGenCfg(unsigned short usDspBaseIO, unsigned uIndex,
+ unsigned char ucValue);
+unsigned char dsp3780I_ReadGenCfg(unsigned short usDspBaseIO,
+ unsigned uIndex);
+int dsp3780I_GetIPCSource(unsigned short usDspBaseIO,
+ unsigned short *pusIPCSource);
+
+/* I/O port access macros */
+#define MKWORD(var) (*((unsigned short *)(&var)))
+#define MKBYTE(var) (*((unsigned char *)(&var)))
+
+#define WriteMsaCfg(addr,value) dsp3780I_WriteMsaCfg(usDspBaseIO,addr,value)
+#define ReadMsaCfg(addr) dsp3780I_ReadMsaCfg(usDspBaseIO,addr)
+#define WriteGenCfg(index,value) dsp3780I_WriteGenCfg(usDspBaseIO,index,value)
+#define ReadGenCfg(index) dsp3780I_ReadGenCfg(usDspBaseIO,index)
+
+#define InWordDsp(index) inw(usDspBaseIO+index)
+#define InByteDsp(index) inb(usDspBaseIO+index)
+#define OutWordDsp(index,value) outw(value,usDspBaseIO+index)
+#define OutByteDsp(index,value) outb(value,usDspBaseIO+index)
+
+#endif
diff -u --recursive --new-file v2.4.10/linux/drivers/char/mwave/Makefile linux/drivers/char/mwave/Makefile
--- v2.4.10/linux/drivers/char/mwave/Makefile Wed Dec 31 16:00:00 1969
+++ linux/drivers/char/mwave/Makefile Sun Sep 30 12:26:05 2001
@@ -0,0 +1,25 @@
+#
+# Makefile for ACP Modem (Mwave).
+#
+# See the README file in this directory for more info. <pau...@us.ibm.com>
+#
+# Note! Dependencies are done automagically by 'make dep', which also
+# removes any old dependencies. DON'T put your own dependencies here
+# unless it's something special (ie not a .c file).
+#
+# Note 2! The CFLAGS definitions are now inherited from the
+# parent makes..
+#
+
+# To compile in lots (~20 KiB) of run-time enablable printk()s for debugging:
+EXTRA_CFLAGS += -DMW_TRACE
+
+# To have the mwave driver disable other uarts if necessary
+# EXTRA_CFLAGS += -DMWAVE_FUTZ_WITH_OTHER_DEVICES
+
+O_TARGET := mwave.o
+
+obj-y := mwavedd.o smapi.o tp3780i.o 3780i.o
+obj-m := $(O_TARGET)
+
+include $(TOPDIR)/Rules.make
diff -u --recursive --new-file v2.4.10/linux/drivers/char/mwave/README linux/drivers/char/mwave/README
--- v2.4.10/linux/drivers/char/mwave/README Wed Dec 31 16:00:00 1969
+++ linux/drivers/char/mwave/README Sun Sep 30 12:26:05 2001
@@ -0,0 +1,50 @@
+Module options
+--------------
+
+The mwave module takes the following options. Note that these options
+are not saved by the BIOS and so do not persist after unload and reload.
+
+ mwave_debug=value, where value is bitwise OR of trace flags:
+ 0x0001 mwavedd api tracing
+ 0x0002 smapi api tracing
+ 0x0004 3780i tracing
+ 0x0008 tp3780i tracing
+
+ Tracing only occurs if the driver has been compiled with the
+ MW_TRACE macro #defined (i.e. let EXTRA_CFLAGS += -DMW_TRACE
+ in the Makefile).
+
+ mwave_3780i_irq=5/7/10/11/15
+ If the dsp irq has not been setup and stored in bios by the
+ thinkpad configuration utility then this parameter allows the
+ irq used by the dsp to be configured.
+
+ mwave_3780i_io=0x130/0x350/0x0070/0xDB0
+ If the dsp io range has not been setup and stored in bios by the
+ thinkpad configuration utility then this parameter allows the
+ io range used by the dsp to be configured.
+
+ mwave_uart_irq=3/4
+ If the mwave's uart irq has not been setup and stored in bios by the
+ thinkpad configuration utility then this parameter allows the
+ irq used by the mwave uart to be configured.
+
+ mwave_uart_io=0x3f8/0x2f8/0x3E8/0x2E8
+ If the uart io range has not been setup and stored in bios by the
+ thinkpad configuration utility then this parameter allows the
+ io range used by the mwave uart to be configured.
+
+Example to enable the 3780i DSP using ttyS1 resources:
+
+ insmod mwave mwave_3780i_irq=10 mwave_3780i_io=0x0130 mwave_uart_irq=3 mwave_uart_io=0x2f8
+
+Accessing the driver
+--------------------
+
+You must also create a node for the driver. Without devfs:
+ mkdir -p /dev/modems
+ mknod --mode=660 /dev/modems/mwave c 10 219
+With devfs:
+ mkdir -p /dev/modems
+ ln -s ../misc/mwave /dev/modems/mwave
+
diff -u --recursive --new-file v2.4.10/linux/drivers/char/mwave/mwavedd.c linux/drivers/char/mwave/mwavedd.c
--- v2.4.10/linux/drivers/char/mwave/mwavedd.c Wed Dec 31 16:00:00 1969
+++ linux/drivers/char/mwave/mwavedd.c Sun Sep 30 12:26:05 2001
@@ -0,0 +1,638 @@
+/*
+*
+* mwavedd.c -- mwave device driver
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/fs.h>
+#include <linux/init.h>
+#include <linux/major.h>
+#include <linux/miscdevice.h>
+#include <linux/proc_fs.h>
+#include <linux/serial.h>
+#include <linux/sched.h>
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)
+#include <linux/spinlock.h>
+#else
+#include <asm/spinlock.h>
+#endif
+#include <linux/delay.h>
+#include "smapi.h"
+#include "mwavedd.h"
+#include "3780i.h"
+#include "tp3780i.h"
+
+#ifndef __exit
+#define __exit
+#endif
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)
+static int mwave_get_info(char *buf, char **start, off_t offset, int len);
+#else
+static int mwave_read_proc(char *buf, char **start, off_t offset, int xlen, int unused);
+static struct proc_dir_entry mwave_proc = {
+ 0, /* unsigned short low_ino */
+ 5, /* unsigned short namelen */
+ "mwave", /* const char *name */
+ S_IFREG | S_IRUGO, /* mode_t mode */
+ 1, /* nlink_t nlink */
+ 0, /* uid_t uid */
+ 0, /* gid_t gid */
+ 0, /* unsigned long size */
+ NULL, /* struct inode_operations *ops */
+ &mwave_read_proc /* int (*get_info) (...) */
+};
+#endif
+
+/*
+* These parameters support the setting of MWave resources. Note that no
+* checks are made against other devices (ie. superio) for conflicts.
+* We'll depend on users using the tpctl utility to do that for now
+*/
+int mwave_debug = 0;
+int mwave_3780i_irq = 0;
+int mwave_3780i_io = 0;
+int mwave_uart_irq = 0;
+int mwave_uart_io = 0;
+MODULE_PARM(mwave_debug, "i");
+MODULE_PARM(mwave_3780i_irq, "i");
+MODULE_PARM(mwave_3780i_io, "i");
+MODULE_PARM(mwave_uart_irq, "i");
+MODULE_PARM(mwave_uart_io, "i");
+
+static int mwave_open(struct inode *inode, struct file *file);
+static int mwave_close(struct inode *inode, struct file *file);
+static int mwave_ioctl(struct inode *inode, struct file *filp,
+ unsigned int iocmd, unsigned long ioarg);
+
+MWAVE_DEVICE_DATA mwave_s_mdd;
+
+static int mwave_open(struct inode *inode, struct file *file)
+{
+ unsigned int retval = 0;
+
+ PRINTK_3(TRACE_MWAVE,
+ "mwavedd::mwave_open, entry inode %x file %x\n",
+ (int) inode, (int) file);
+ PRINTK_2(TRACE_MWAVE,
+ "mwavedd::mwave_open, exit return retval %x\n", retval);
+
+ MOD_INC_USE_COUNT;
+ return retval;
+}
+
+static int mwave_close(struct inode *inode, struct file *file)
+{
+ unsigned int retval = 0;
+
+ PRINTK_3(TRACE_MWAVE,
+ "mwavedd::mwave_close, entry inode %x file %x\n",
+ (int) inode, (int) file);
+
+ PRINTK_2(TRACE_MWAVE, "mwavedd::mwave_close, exit retval %x\n",
+ retval);
+
+ MOD_DEC_USE_COUNT;
+ return retval;
+}
+
+static int mwave_ioctl(struct inode *inode, struct file *file,
+ unsigned int iocmd, unsigned long ioarg)
+{
+ unsigned int retval = 0;
+ pMWAVE_DEVICE_DATA pDrvData = &mwave_s_mdd;
+
+ PRINTK_5(TRACE_MWAVE,
+ "mwavedd::mwave_ioctl, entry inode %x file %x cmd %x arg %x\n",
+ (int) inode, (int) file, iocmd, (int) ioarg);
+
+ switch (iocmd) {
+
+ case IOCTL_MW_RESET:
+ PRINTK_1(TRACE_MWAVE,
+ "mwavedd::mwave_ioctl, IOCTL_MW_RESET calling tp3780I_ResetDSP\n");
+ retval = tp3780I_ResetDSP(&pDrvData->rBDData);
+ PRINTK_2(TRACE_MWAVE,
+ "mwavedd::mwave_ioctl, IOCTL_MW_RESET retval %x from tp3780I_ResetDSP\n",
+ retval);
+ break;
+
+ case IOCTL_MW_RUN:
+ PRINTK_1(TRACE_MWAVE,
+ "mwavedd::mwave_ioctl, IOCTL_MW_RUN calling tp3780I_StartDSP\n");
+ retval = tp3780I_StartDSP(&pDrvData->rBDData);
+ PRINTK_2(TRACE_MWAVE,
+ "mwavedd::mwave_ioctl, IOCTL_MW_RUN retval %x from tp3780I_StartDSP\n",
+ retval);
+ break;
+
+ case IOCTL_MW_DSP_ABILITIES: {
+ MW_ABILITIES rAbilities;
+
+ PRINTK_1(TRACE_MWAVE,
+ "mwavedd::mwave_ioctl, IOCTL_MW_DSP_ABILITIES calling tp3780I_QueryAbilities\n");
+ retval = tp3780I_QueryAbilities(&pDrvData->rBDData, &rAbilities);
+ PRINTK_2(TRACE_MWAVE,
+ "mwavedd::mwave_ioctl, IOCTL_MW_DSP_ABILITIES retval %x from tp3780I_QueryAbilities\n",
+ retval);
+ if (retval == 0) {
+ if( copy_to_user((char *) ioarg, (char *) &rAbilities, sizeof(MW_ABILITIES)) )
+ return -EFAULT;
+ }
+ PRINTK_2(TRACE_MWAVE,
+ "mwavedd::mwave_ioctl, IOCTL_MW_DSP_ABILITIES exit retval %x\n",
+ retval);
+ }
+ break;
+
+ case IOCTL_MW_READ_DATA:
+ case IOCTL_MW_READCLEAR_DATA: {
+ MW_READWRITE rReadData;
+ unsigned short *pusBuffer = 0;
+
+ if( copy_from_user((char *) &rReadData, (char *) ioarg, sizeof(MW_READWRITE)) )
+ return -EFAULT;
+ pusBuffer = (unsigned short *) (rReadData.pBuf);
+
+ PRINTK_4(TRACE_MWAVE,
+ "mwavedd::mwave_ioctl IOCTL_MW_READ_DATA, size %lx, ioarg %lx pusBuffer %p\n",
+ rReadData.ulDataLength, ioarg, pusBuffer);
+ retval = tp3780I_ReadWriteDspDStore(&pDrvData->rBDData, iocmd,
+ (void *) pusBuffer, rReadData.ulDataLength, rReadData.usDspAddress);
+ }
+ break;
+
+ case IOCTL_MW_READ_INST: {
+ MW_READWRITE rReadData;
+ unsigned short *pusBuffer = 0;
+
+ if( copy_from_user((char *) &rReadData, (char *) ioarg, sizeof(MW_READWRITE)) )
+ return -EFAULT;
+ pusBuffer = (unsigned short *) (rReadData.pBuf);
+
+ PRINTK_4(TRACE_MWAVE,
+ "mwavedd::mwave_ioctl IOCTL_MW_READ_INST, size %lx, ioarg %lx pusBuffer %p\n",
+ rReadData.ulDataLength / 2, ioarg,
+ pusBuffer);
+ retval = tp3780I_ReadWriteDspDStore(&pDrvData->rBDData,
+ iocmd, pusBuffer,
+ rReadData.ulDataLength / 2,
+ rReadData.usDspAddress);
+ }
+ break;
+
+ case IOCTL_MW_WRITE_DATA: {
+ MW_READWRITE rWriteData;
+ unsigned short *pusBuffer = 0;
+
+ if( copy_from_user((char *) &rWriteData, (char *) ioarg, sizeof(MW_READWRITE)) )
+ return -EFAULT;
+ pusBuffer = (unsigned short *) (rWriteData.pBuf);
+
+ PRINTK_4(TRACE_MWAVE,
+ "mwavedd::mwave_ioctl IOCTL_MW_WRITE_DATA, size %lx, ioarg %lx pusBuffer %p\n",
+ rWriteData.ulDataLength, ioarg,
+ pusBuffer);
+ retval = tp3780I_ReadWriteDspDStore(&pDrvData->rBDData, iocmd,
+ pusBuffer, rWriteData.ulDataLength, rWriteData.usDspAddress);
+ }
+ break;
+
+ case IOCTL_MW_WRITE_INST: {
+ MW_READWRITE rWriteData;
+ unsigned short *pusBuffer = 0;
+
+ if( copy_from_user((char *) &rWriteData, (char *) ioarg, sizeof(MW_READWRITE)) )
+ return -EFAULT;
+ pusBuffer = (unsigned short *) (rWriteData.pBuf);
+
+ PRINTK_4(TRACE_MWAVE,
+ "mwavedd::mwave_ioctl IOCTL_MW_WRITE_INST, size %lx, ioarg %lx pusBuffer %p\n",
+ rWriteData.ulDataLength, ioarg,
+ pusBuffer);
+ retval = tp3780I_ReadWriteDspIStore(&pDrvData->rBDData, iocmd,
+ pusBuffer, rWriteData.ulDataLength, rWriteData.usDspAddress);
+ }
+ break;
+
+ case IOCTL_MW_REGISTER_IPC: {
+ unsigned int ipcnum = (unsigned int) ioarg;
+
+ PRINTK_3(TRACE_MWAVE,
+ "mwavedd::mwave_ioctl IOCTL_MW_REGISTER_IPC ipcnum %x entry usIntCount %x\n",
+ ipcnum,
+ pDrvData->IPCs[ipcnum].usIntCount);
+
+ if (ipcnum > 16) {
+ PRINTK_ERROR(KERN_ERR_MWAVE "mwavedd::mwave_ioctl: IOCTL_MW_REGISTER_IPC: Error: Invalid ipcnum %x\n", ipcnum);
+ return -EINVAL;
+ }
+ pDrvData->IPCs[ipcnum].bIsHere = FALSE;
+ pDrvData->IPCs[ipcnum].bIsEnabled = TRUE;
+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)
+ current->nice = -20; /* boost to provide priority timing */
+ #else
+ current->priority = 0x28; /* boost to provide priority timing */
+ #endif
+
+ PRINTK_2(TRACE_MWAVE,
+ "mwavedd::mwave_ioctl IOCTL_MW_REGISTER_IPC ipcnum %x exit\n",
+ ipcnum);
+ }
+ break;
+
+ case IOCTL_MW_GET_IPC: {
+ unsigned int ipcnum = (unsigned int) ioarg;
+ spinlock_t ipc_lock = SPIN_LOCK_UNLOCKED;
+ unsigned long flags;
+
+ PRINTK_3(TRACE_MWAVE,
+ "mwavedd::mwave_ioctl IOCTL_MW_GET_IPC ipcnum %x, usIntCount %x\n",
+ ipcnum,
+ pDrvData->IPCs[ipcnum].usIntCount);
+ if (ipcnum > 16) {
+ PRINTK_ERROR(KERN_ERR_MWAVE "mwavedd::mwave_ioctl: IOCTL_MW_GET_IPC: Error: Invalid ipcnum %x\n", ipcnum);
+ return -EINVAL;
+ }
+
+ if (pDrvData->IPCs[ipcnum].bIsEnabled == TRUE) {
+ PRINTK_2(TRACE_MWAVE,
+ "mwavedd::mwave_ioctl, thread for ipc %x going to sleep\n",
+ ipcnum);
+
+ spin_lock_irqsave(&ipc_lock, flags);
+ /* check whether an event was signalled by */
+ /* the interrupt handler while we were gone */
+ if (pDrvData->IPCs[ipcnum].usIntCount == 1) { /* first int has occurred (race condition) */
+ pDrvData->IPCs[ipcnum].usIntCount = 2; /* first int has been handled */
+ spin_unlock_irqrestore(&ipc_lock, flags);
+ PRINTK_2(TRACE_MWAVE,
+ "mwavedd::mwave_ioctl IOCTL_MW_GET_IPC ipcnum %x handling first int\n",
+ ipcnum);
+ } else { /* either 1st int has not yet occurred, or we have already handled the first int */
+ pDrvData->IPCs[ipcnum].bIsHere = TRUE;
+ interruptible_sleep_on(&pDrvData->IPCs[ipcnum].ipc_wait_queue);
+ pDrvData->IPCs[ipcnum].bIsHere = FALSE;
+ if (pDrvData->IPCs[ipcnum].usIntCount == 1) {
+ pDrvData->IPCs[ipcnum].
+ usIntCount = 2;
+ }
+ spin_unlock_irqrestore(&ipc_lock, flags);
+ PRINTK_2(TRACE_MWAVE,
+ "mwavedd::mwave_ioctl IOCTL_MW_GET_IPC ipcnum %x woke up and returning to application\n",
+ ipcnum);
+ }
+ PRINTK_2(TRACE_MWAVE,
+ "mwavedd::mwave_ioctl IOCTL_MW_GET_IPC, returning thread for ipc %x processing\n",
+ ipcnum);
+ }
+ }
+ break;
+
+ case IOCTL_MW_UNREGISTER_IPC: {
+ unsigned int ipcnum = (unsigned int) ioarg;
+
+ PRINTK_2(TRACE_MWAVE,
+ "mwavedd::mwave_ioctl IOCTL_MW_UNREGISTER_IPC ipcnum %x\n",
+ ipcnum);
+ if (ipcnum > 16) {
+ PRINTK_ERROR(KERN_ERR_MWAVE "mwavedd::mwave_ioctl: IOCTL_MW_UNREGISTER_IPC: Error: Invalid ipcnum %x\n", ipcnum);
+ return -EINVAL;
+ }
+ if (pDrvData->IPCs[ipcnum].bIsEnabled == TRUE) {
+ pDrvData->IPCs[ipcnum].bIsEnabled = FALSE;
+ if (pDrvData->IPCs[ipcnum].bIsHere == TRUE) {
+ wake_up_interruptible(&pDrvData->IPCs[ipcnum].ipc_wait_queue);
+ }
+ }
+ }
+ break;
+
+ default:
+ PRINTK_ERROR(KERN_ERR_MWAVE "mwavedd::mwave_ioctl: Error: Unrecognized iocmd %x\n", iocmd);
+ return -ENOTTY;
+ break;
+ } /* switch */
+
+ PRINTK_2(TRACE_MWAVE, "mwavedd::mwave_ioctl, exit retval %x\n", retval);
+
+ return retval;
+}
+
+
+static ssize_t mwave_read(struct file *file, char *buf, size_t count,
+ loff_t * ppos)
+{
+ PRINTK_5(TRACE_MWAVE,
+ "mwavedd::mwave_read entry file %p, buf %p, count %x ppos %p\n",
+ file, buf, count, ppos);
+
+ return -EINVAL;
+}
+
+
+static ssize_t mwave_write(struct file *file, const char *buf,
+ size_t count, loff_t * ppos)
+{
+ PRINTK_5(TRACE_MWAVE,
+ "mwavedd::mwave_write entry file %p, buf %p, count %x ppos %p\n",
+ file, buf, count, ppos);
+
+ return -EINVAL;
+}
+
+
+static int register_serial_portandirq(unsigned int port, int irq)
+{
+ struct serial_struct serial;
+
+ switch ( port ) {
+ case 0x3f8:
+ case 0x2f8:
+ case 0x3e8:
+ case 0x2e8:
+ /* OK */
+ break;
+ default:
+ PRINTK_ERROR(KERN_ERR_MWAVE "mwavedd::register_serial_portandirq: Error: Illegal port %x\n", port );
+ return -1;
+ } /* switch */
+ /* port is okay */
+
+ switch ( irq ) {
+ case 3:
+ case 4:
+ case 5:
+ case 7:
+ /* OK */
+ break;
+ default:
+ PRINTK_ERROR(KERN_ERR_MWAVE "mwavedd::register_serial_portandirq: Error: Illegal irq %x\n", irq );
+ return -1;
+ } /* switch */
+ /* irq is okay */
+
+ memset(&serial, 0, sizeof(serial));
+ serial.port = port;
+ serial.irq = irq;
+ serial.flags = ASYNC_SHARE_IRQ;
+
+ return register_serial(&serial);
+}
+
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)
+static struct file_operations mwave_fops = {
+ owner:THIS_MODULE,
+ read:mwave_read,
+ write:mwave_write,
+ ioctl:mwave_ioctl,
+ open:mwave_open,
+ release:mwave_close
+};
+#else
+static struct file_operations mwave_fops = {
+ NULL, /* lseek */
+ mwave_read, /* read */
+ mwave_write, /* write */
+ NULL, /* readdir */
+ NULL, /* poll */
+ mwave_ioctl, /* ioctl */
+ NULL, /* mmap */
+ mwave_open, /* open */
+ NULL, /* flush */
+ mwave_close /* release */
+};
+#endif
+
+static struct miscdevice mwave_misc_dev = { MWAVE_MINOR, "mwave", &mwave_fops };
+
+/*
+* mwave_init is called on module load
+*
+* mwave_exit is called on module unload
+* mwave_exit is also used to clean up after an aborted mwave_init
+*/
+static void __exit mwave_exit(void)
+{
+ pMWAVE_DEVICE_DATA pDrvData = &mwave_s_mdd;
+
+ PRINTK_1(TRACE_MWAVE, "mwavedd::mwave_exit entry\n");
+
+ if (pDrvData->bProcEntryCreated) {
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)
+ remove_proc_entry("mwave", NULL);
+#else
+ proc_unregister(&proc_root, mwave_proc.low_ino);
+#endif
+ }
+ if ( pDrvData->sLine >= 0 ) {
+ unregister_serial(pDrvData->sLine);
+ }
+ if (pDrvData->bMwaveDevRegistered) {
+ misc_deregister(&mwave_misc_dev);
+ }
+ if (pDrvData->bDSPEnabled) {
+ tp3780I_DisableDSP(&pDrvData->rBDData);
+ }
+ if (pDrvData->bResourcesClaimed) {
+ tp3780I_ReleaseResources(&pDrvData->rBDData);
+ }
+ if (pDrvData->bBDInitialized) {
+ tp3780I_Cleanup(&pDrvData->rBDData);
+ }
+
+ PRINTK_1(TRACE_MWAVE, "mwavedd::mwave_exit exit\n");
+}
+
+module_exit(mwave_exit);
+
+static int __init mwave_init(void)
+{
+ int i;
+ int retval = 0;
+ unsigned int resultMiscRegister;
+ pMWAVE_DEVICE_DATA pDrvData = &mwave_s_mdd;
+
+ memset(&mwave_s_mdd, 0, sizeof(MWAVE_DEVICE_DATA));
+
+ PRINTK_1(TRACE_MWAVE, "mwavedd::mwave_init entry\n");
+
+ pDrvData->bBDInitialized = FALSE;
+ pDrvData->bResourcesClaimed = FALSE;
+ pDrvData->bDSPEnabled = FALSE;
+ pDrvData->bDSPReset = FALSE;
+ pDrvData->bMwaveDevRegistered = FALSE;
+ pDrvData->sLine = -1;
+ pDrvData->bProcEntryCreated = FALSE;
+
+ for (i = 0; i < 16; i++) {
+ pDrvData->IPCs[i].bIsEnabled = FALSE;
+ pDrvData->IPCs[i].bIsHere = FALSE;
+ pDrvData->IPCs[i].usIntCount = 0; /* no ints received yet */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)
+ init_waitqueue_head(&pDrvData->IPCs[i].ipc_wait_queue);
+#endif
+ }
+
+ retval = tp3780I_InitializeBoardData(&pDrvData->rBDData);
+ PRINTK_2(TRACE_MWAVE,
+ "mwavedd::mwave_init, return from tp3780I_InitializeBoardData retval %x\n",
+ retval);
+ if (retval) {
+ PRINTK_ERROR(KERN_ERR_MWAVE "mwavedd::mwave_init: Error: Failed to initialize board data\n");
+ goto cleanup_error;
+ }
+ pDrvData->bBDInitialized = TRUE;
+
+ retval = tp3780I_CalcResources(&pDrvData->rBDData);
+ PRINTK_2(TRACE_MWAVE,
+ "mwavedd::mwave_init, return from tp3780I_CalcResources retval %x\n",
+ retval);
+ if (retval) {
+ PRINTK_ERROR(KERN_ERR_MWAVE "mwavedd:mwave_init: Error: Failed to calculate resources\n");
+ goto cleanup_error;
+ }
+
+ retval = tp3780I_ClaimResources(&pDrvData->rBDData);
+ PRINTK_2(TRACE_MWAVE,
+ "mwavedd::mwave_init, return from tp3780I_ClaimResources retval %x\n",
+ retval);
+ if (retval) {
+ PRINTK_ERROR(KERN_ERR_MWAVE "mwavedd:mwave_init: Error: Failed to claim resources\n");
+ goto cleanup_error;
+ }
+ pDrvData->bResourcesClaimed = TRUE;
+
+ retval = tp3780I_EnableDSP(&pDrvData->rBDData);
+ PRINTK_2(TRACE_MWAVE,
+ "mwavedd::mwave_init, return from tp3780I_EnableDSP retval %x\n",
+ retval);
+ if (retval) {
+ PRINTK_ERROR(KERN_ERR_MWAVE "mwavedd:mwave_init: Error: Failed to enable DSP\n");
+ goto cleanup_error;
+ }
+ pDrvData->bDSPEnabled = TRUE;
+
+ resultMiscRegister = misc_register(&mwave_misc_dev);
+ if (resultMiscRegister < 0) {
+ PRINTK_ERROR(KERN_ERR_MWAVE "mwavedd:mwave_init: Error: Failed to register misc device\n");
+ goto cleanup_error;
+ }
+ pDrvData->bMwaveDevRegistered = TRUE;
+
+ pDrvData->sLine = register_serial_portandirq(
+ pDrvData->rBDData.rDspSettings.usUartBaseIO,
+ pDrvData->rBDData.rDspSettings.usUartIrq
+ );
+ if (pDrvData->sLine < 0) {
+ PRINTK_ERROR(KERN_ERR_MWAVE "mwavedd:mwave_init: Error: Failed to register serial driver\n");
+ goto cleanup_error;
+ }
+ /* uart is registered */
+
+ if (
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)
+ !create_proc_info_entry("mwave", 0, NULL, mwave_get_info)
+#else
+ proc_register(&proc_root, &mwave_proc)
+#endif
+ ) {
+ PRINTK_ERROR(KERN_ERR_MWAVE "mwavedd::mwave_init: Error: Failed to register /proc/mwave\n");
+ goto cleanup_error;
+ }
+ pDrvData->bProcEntryCreated = TRUE;
+
+ /* SUCCESS! */
+ return 0;
+
+ cleanup_error:
+ PRINTK_ERROR(KERN_ERR_MWAVE "mwavedd::mwave_init: Error: Failed to initialize\n");
+ mwave_exit(); /* clean up */
+
+ return -EIO;
+}
+
+module_init(mwave_init);
+
+
+/*
+* proc entry stuff added by Ian Pilcher <pil...@us.ibm.com>
+*/
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)
+static int mwave_get_info(char *buf, char **start, off_t offset, int len)
+{
+ DSP_3780I_CONFIG_SETTINGS *pSettings = &mwave_s_mdd.rBDData.rDspSettings;
+
+ char *out = buf;
+
+ out += sprintf(out, "3780i_IRQ %i\n", pSettings->usDspIrq);
+ out += sprintf(out, "3780i_DMA %i\n", pSettings->usDspDma);
+ out += sprintf(out, "3780i_IO %#.4x\n", pSettings->usDspBaseIO);
+ out += sprintf(out, "UART_IRQ %i\n", pSettings->usUartIrq);
+ out += sprintf(out, "UART_IO %#.4x\n", pSettings->usUartBaseIO);
+
+ return out - buf;
+}
+#else /* kernel version < 2.4.0 */
+static int mwave_read_proc(char *buf, char **start, off_t offset,
+ int xlen, int unused)
+{
+ DSP_3780I_CONFIG_SETTINGS *pSettings = &mwave_s_mdd.rBDData.rDspSettings;
+ int len;
+
+ len = sprintf(buf, "3780i_IRQ %i\n", pSettings->usDspIrq);
+ len += sprintf(&buf[len], "3780i_DMA %i\n", pSettings->usDspDma);
+ len += sprintf(&buf[len], "3780i_IO %#.4x\n", pSettings->usDspBaseIO);
+ len += sprintf(&buf[len], "UART_IRQ %i\n", pSettings->usUartIrq);
+ len += sprintf(&buf[len], "UART_IO %#.4x\n", pSettings->usUartBaseIO);
+
+ return len;
+}
+#endif
diff -u --recursive --new-file v2.4.10/linux/drivers/char/mwave/mwavedd.h linux/drivers/char/mwave/mwavedd.h
--- v2.4.10/linux/drivers/char/mwave/mwavedd.h Wed Dec 31 16:00:00 1969
+++ linux/drivers/char/mwave/mwavedd.h Sun Sep 30 12:26:05 2001
@@ -0,0 +1,151 @@
+/*
+*
+* mwavedd.h -- declarations for mwave device driver
+#ifndef _LINUX_MWAVEDD_H
+#define _LINUX_MWAVEDD_H
+#include "3780i.h"
+#include "tp3780i.h"
+#include "mwavepub.h"
+#include <linux/ioctl.h>
+#include <asm/uaccess.h>
+
+extern int mwave_debug;
+extern int mwave_3780i_irq;
+extern int mwave_3780i_io;
+extern int mwave_uart_irq;
+extern int mwave_uart_io;
+
+#define PRINTK_ERROR printk
+#define KERN_ERR_MWAVE KERN_ERR "mwave: "
+
+#define TRACE_MWAVE 0x0001
+#define TRACE_SMAPI 0x0002
+#define TRACE_3780I 0x0004
+#define TRACE_TP3780I 0x0008
+
+#ifdef MW_TRACE
+#define PRINTK_1(f,s) \
+ if (f & (mwave_debug)) { \
+ printk(s); \
+ }
+
+#define PRINTK_2(f,s,v1) \
+ if (f & (mwave_debug)) { \
+ printk(s,v1); \
+ }
+
+#define PRINTK_3(f,s,v1,v2) \
+ if (f & (mwave_debug)) { \
+ printk(s,v1,v2); \
+ }
+
+#define PRINTK_4(f,s,v1,v2,v3) \
+ if (f & (mwave_debug)) { \
+ printk(s,v1,v2,v3); \
+ }
+
+#define PRINTK_5(f,s,v1,v2,v3,v4) \
+ if (f & (mwave_debug)) { \
+ printk(s,v1,v2,v3,v4); \
+ }
+
+#define PRINTK_6(f,s,v1,v2,v3,v4,v5) \
+ if (f & (mwave_debug)) { \
+ printk(s,v1,v2,v3,v4,v5); \
+ }
+
+#define PRINTK_7(f,s,v1,v2,v3,v4,v5,v6) \
+ if (f & (mwave_debug)) { \
+ printk(s,v1,v2,v3,v4,v5,v6); \
+ }
+
+#define PRINTK_8(f,s,v1,v2,v3,v4,v5,v6,v7) \
+ if (f & (mwave_debug)) { \
+ printk(s,v1,v2,v3,v4,v5,v6,v7); \
+ }
+
+#else
+#define PRINTK_1(f,s)
+#define PRINTK_2(f,s,v1)
+#define PRINTK_3(f,s,v1,v2)
+#define PRINTK_4(f,s,v1,v2,v3)
+#define PRINTK_5(f,s,v1,v2,v3,v4)
+#define PRINTK_6(f,s,v1,v2,v3,v4,v5)
+#define PRINTK_7(f,s,v1,v2,v3,v4,v5,v6)
+#define PRINTK_8(f,s,v1,v2,v3,v4,v5,v6,v7)
+#endif
+
+
+typedef struct _MWAVE_IPC {
+ unsigned short usIntCount; /* 0=none, 1=first, 2=greater than 1st */
+ BOOLEAN bIsEnabled;
+ BOOLEAN bIsHere;
+ /* entry spin lock */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)
+ wait_queue_head_t ipc_wait_queue;
+#else
+ struct wait_queue *ipc_wait_queue;
+#endif
+} MWAVE_IPC;
+
+typedef struct _MWAVE_DEVICE_DATA {
+ THINKPAD_BD_DATA rBDData; /* board driver's data area */
+ unsigned long ulIPCSource_ISR; /* IPC source bits for recently processed intr, set during ISR processing */
+ unsigned long ulIPCSource_DPC; /* IPC source bits for recently processed intr, set during DPC processing */
+ BOOLEAN bBDInitialized;
+ BOOLEAN bResourcesClaimed;
+ BOOLEAN bDSPEnabled;
+ BOOLEAN bDSPReset;
+ MWAVE_IPC IPCs[16];
+ BOOLEAN bMwaveDevRegistered;
+ BOOLEAN bProcEntryCreated;
+ short sLine;
+
+} MWAVE_DEVICE_DATA, *pMWAVE_DEVICE_DATA;
+
+#endif
diff -u --recursive --new-file v2.4.10/linux/drivers/char/mwave/mwavepub.h linux/drivers/char/mwave/mwavepub.h
--- v2.4.10/linux/drivers/char/mwave/mwavepub.h Wed Dec 31 16:00:00 1969
+++ linux/drivers/char/mwave/mwavepub.h Sun Sep 30 12:26:05 2001
@@ -0,0 +1,94 @@
+/*
+*
+* mwavepub.h -- PUBLIC declarations for the mwave driver
+* and applications using it
+#ifndef _LINUX_MWAVEPUB_H
+#define _LINUX_MWAVEPUB_H
+
+#ifndef MWAVEM_APP_DIST
+#include <linux/miscdevice.h>
+#endif
+
+#ifdef MWAVEM_APP_DIST
+#define MWAVE_MINOR 219
+#endif
+
+typedef struct _MW_ABILITIES {
+ unsigned long instr_per_sec;
+ unsigned long data_size;
+ unsigned long inst_size;
+ unsigned long bus_dma_bw;
+ unsigned short uart_enable;
+ short component_count;
+ unsigned long component_list[7];
+ char mwave_os_name[16];
+ char bios_task_name[16];
+} MW_ABILITIES, *pMW_ABILITIES;
+
+
+typedef struct _MW_READWRITE {
+ unsigned short usDspAddress; /* The dsp address */
+ unsigned long ulDataLength; /* The size in bytes of the data or user buffer */
+ void *pBuf; /* Input:variable sized buffer */
+} MW_READWRITE, *pMW_READWRITE;
+
+#define IOCTL_MW_RESET _IO(MWAVE_MINOR,1)
+#define IOCTL_MW_RUN _IO(MWAVE_MINOR,2)
+#define IOCTL_MW_DSP_ABILITIES _IOR(MWAVE_MINOR,3,MW_ABILITIES)
+#define IOCTL_MW_READ_DATA _IOR(MWAVE_MINOR,4,MW_READWRITE)
+#define IOCTL_MW_READCLEAR_DATA _IOR(MWAVE_MINOR,5,MW_READWRITE)
+#define IOCTL_MW_READ_INST _IOR(MWAVE_MINOR,6,MW_READWRITE)
+#define IOCTL_MW_WRITE_DATA _IOW(MWAVE_MINOR,7,MW_READWRITE)
+#define IOCTL_MW_WRITE_INST _IOW(MWAVE_MINOR,8,MW_READWRITE)
+#define IOCTL_MW_REGISTER_IPC _IOW(MWAVE_MINOR,9,int)
+#define IOCTL_MW_UNREGISTER_IPC _IOW(MWAVE_MINOR,10,int)
+#define IOCTL_MW_GET_IPC _IOW(MWAVE_MINOR,11,int)
+#define IOCTL_MW_TRACE _IOR(MWAVE_MINOR,12,MW_READWRITE)
+
+
+#endif
diff -u --recursive --new-file v2.4.10/linux/drivers/char/mwave/smapi.c linux/drivers/char/mwave/smapi.c
--- v2.4.10/linux/drivers/char/mwave/smapi.c Wed Dec 31 16:00:00 1969
+++ linux/drivers/char/mwave/smapi.c Sun Sep 30 12:26:05 2001
@@ -0,0 +1,563 @@
+/*
+*
+* smapi.c -- SMAPI interface routines
+#include <linux/kernel.h>
+#include <linux/mc146818rtc.h> /* CMOS defines */
+#include "smapi.h"
+#include "mwavedd.h"
+
+static unsigned short g_usSmapiPort = 0;
+
+
+int smapi_request(unsigned short inBX, unsigned short inCX,
+ unsigned short inDI, unsigned short inSI,
+ unsigned short *outAX, unsigned short *outBX,
+ unsigned short *outCX, unsigned short *outDX,
+ unsigned short *outDI, unsigned short *outSI)
+{
+ unsigned short myoutAX = 2, *pmyoutAX = &myoutAX;
+ unsigned short myoutBX = 3, *pmyoutBX = &myoutBX;
+ unsigned short myoutCX = 4, *pmyoutCX = &myoutCX;
+ unsigned short myoutDX = 5, *pmyoutDX = &myoutDX;
+ unsigned short myoutDI = 6, *pmyoutDI = &myoutDI;
+ unsigned short myoutSI = 7, *pmyoutSI = &myoutSI;
+ unsigned short usSmapiOK = -EIO, *pusSmapiOK = &usSmapiOK;
+ unsigned int inBXCX = (inBX << 16) | inCX;
+ unsigned int inDISI = (inDI << 16) | inSI;
+ int retval = 0;
+
+ PRINTK_5(TRACE_SMAPI, "inBX %x inCX %x inDI %x inSI %x\n",
+ inBX, inCX, inDI, inSI);
+
+ __asm__ __volatile__("movw $0x5380,%%ax\n\t"
+ "movl %7,%%ebx\n\t"
+ "shrl $16, %%ebx\n\t"
+ "movw %7,%%cx\n\t"
+ "movl %8,%%edi\n\t"
+ "shrl $16,%%edi\n\t"
+ "movw %8,%%si\n\t"
+ "movw %9,%%dx\n\t"
+ "out %%al,%%dx\n\t"
+ "out %%al,$0x4F\n\t"
+ "cmpb $0x53,%%ah\n\t"
+ "je 2f\n\t"
+ "1:\n\t"
+ "orb %%ah,%%ah\n\t"
+ "jnz 2f\n\t"
+ "movw %%ax,%0\n\t"
+ "movw %%bx,%1\n\t"
+ "movw %%cx,%2\n\t"
+ "movw %%dx,%3\n\t"
+ "movw %%di,%4\n\t"
+ "movw %%si,%5\n\t"
+ "movw $1,%6\n\t"
+ "2:\n\t":"=m"(*(unsigned short *) pmyoutAX),
+ "=m"(*(unsigned short *) pmyoutBX),
+ "=m"(*(unsigned short *) pmyoutCX),
+ "=m"(*(unsigned short *) pmyoutDX),
+ "=m"(*(unsigned short *) pmyoutDI),
+ "=m"(*(unsigned short *) pmyoutSI),
+ "=m"(*(unsigned short *) pusSmapiOK)
+ :"m"(inBXCX), "m"(inDISI), "m"(g_usSmapiPort)
+ :"%eax", "%ebx", "%ecx", "%edx", "%edi",
+ "%esi");
+
+ PRINTK_8(TRACE_SMAPI,
+ "myoutAX %x myoutBX %x myoutCX %x myoutDX %x myoutDI %x myoutSI %x usSmapiOK %x\n",
+ myoutAX, myoutBX, myoutCX, myoutDX, myoutDI, myoutSI,
+ usSmapiOK);
+ *outAX = myoutAX;
+ *outBX = myoutBX;
+ *outCX = myoutCX;
+ *outDX = myoutDX;
+ *outDI = myoutDI;
+ *outSI = myoutSI;
+
+ retval = (usSmapiOK == 1) ? 0 : -EIO;
+ PRINTK_2(TRACE_SMAPI, "smapi::smapi_request exit retval %x\n", retval);
+ return retval;
+}
+
+
+int smapi_query_DSP_cfg(SMAPI_DSP_SETTINGS * pSettings)
+{
+ int bRC = -EIO;
+ unsigned short usAX, usBX, usCX, usDX, usDI, usSI;
+ unsigned short ausDspBases[] = { 0x0030, 0x4E30, 0x8E30, 0xCE30, 0x0130, 0x0350, 0x0070, 0x0DB0 };
+ unsigned short ausUartBases[] = { 0x03F8, 0x02F8, 0x03E8, 0x02E8 };
+ unsigned short numDspBases = 8;
+ unsigned short numUartBases = 4;
+
+ PRINTK_1(TRACE_SMAPI, "smapi::smapi_query_DSP_cfg entry\n");
+
+ bRC = smapi_request(0x1802, 0x0000, 0, 0,
+ &usAX, &usBX, &usCX, &usDX, &usDI, &usSI);
+ if (bRC) {
+ PRINTK_ERROR(KERN_ERR_MWAVE "smapi::smapi_query_DSP_cfg: Error: Could not get DSP Settings. Aborting.\n");
+ return bRC;
+ }
+
+ PRINTK_1(TRACE_SMAPI, "smapi::smapi_query_DSP_cfg, smapi_request OK\n");
+
+ pSettings->bDSPPresent = ((usBX & 0x0100) != 0);
+ pSettings->bDSPEnabled = ((usCX & 0x0001) != 0);
+ pSettings->usDspIRQ = usSI & 0x00FF;
+ pSettings->usDspDMA = (usSI & 0xFF00) >> 8;
+ if ((usDI & 0x00FF) < numDspBases) {
+ pSettings->usDspBaseIO = ausDspBases[usDI & 0x00FF];
+ } else {
+ pSettings->usDspBaseIO = 0;
+ }
+ PRINTK_6(TRACE_SMAPI,
+ "smapi::smapi_query_DSP_cfg get DSP Settings bDSPPresent %x bDSPEnabled %x usDspIRQ %x usDspDMA %x usDspBaseIO %x\n",
+ pSettings->bDSPPresent, pSettings->bDSPEnabled,
+ pSettings->usDspIRQ, pSettings->usDspDMA,
+ pSettings->usDspBaseIO);
+
+ /* check for illegal values */
+ if ( pSettings->usDspBaseIO == 0 )
+ PRINTK_ERROR(KERN_ERR_MWAVE "smapi::smapi_query_DSP_cfg: Worry: DSP base I/O address is 0\n");
+ if ( pSettings->usDspIRQ == 0 )
+ PRINTK_ERROR(KERN_ERR_MWAVE "smapi::smapi_query_DSP_cfg: Worry: DSP IRQ line is 0\n");
+
+ bRC = smapi_request(0x1804, 0x0000, 0, 0,
+ &usAX, &usBX, &usCX, &usDX, &usDI, &usSI);
+ if (bRC) {
+ PRINTK_ERROR("smapi::smapi_query_DSP_cfg: Error: Could not get DSP modem settings. Aborting.\n");
+ return bRC;
+ }
+
+ PRINTK_1(TRACE_SMAPI, "smapi::smapi_query_DSP_cfg, smapi_request OK\n");
+
+ pSettings->bModemEnabled = ((usCX & 0x0001) != 0);
+ pSettings->usUartIRQ = usSI & 0x000F;
+ if (((usSI & 0xFF00) >> 8) < numUartBases) {
+ pSettings->usUartBaseIO = ausUartBases[(usSI & 0xFF00) >> 8];
+ } else {
+ pSettings->usUartBaseIO = 0;
+ }
+
+ PRINTK_4(TRACE_SMAPI,
+ "smapi::smapi_query_DSP_cfg get DSP modem settings bModemEnabled %x usUartIRQ %x usUartBaseIO %x\n",
+ pSettings->bModemEnabled,
+ pSettings->usUartIRQ,
+ pSettings->usUartBaseIO);
+
+ /* check for illegal values */
+ if ( pSettings->usUartBaseIO == 0 )
+ PRINTK_ERROR(KERN_ERR_MWAVE "smapi::smapi_query_DSP_cfg: Worry: UART base I/O address is 0\n");
+ if ( pSettings->usUartIRQ == 0 )
+ PRINTK_ERROR(KERN_ERR_MWAVE "smapi::smapi_query_DSP_cfg: Worry: UART IRQ line is 0\n");
+
+ PRINTK_2(TRACE_SMAPI, "smapi::smapi_query_DSP_cfg exit bRC %x\n", bRC);
+
+ return bRC;
+}
+
+
+int smapi_set_DSP_cfg(void)
+{
+ int bRC = -EIO;
+ int i;
+ unsigned short usAX, usBX, usCX, usDX, usDI, usSI;
+ unsigned short ausDspBases[] = { 0x0030, 0x4E30, 0x8E30, 0xCE30, 0x0130, 0x0350, 0x0070, 0x0DB0 };
+ unsigned short ausUartBases[] = { 0x03F8, 0x02F8, 0x03E8, 0x02E8 };
+ unsigned short ausDspIrqs[] = { 5, 7, 10, 11, 15 };
+ unsigned short ausUartIrqs[] = { 3, 4 };
+
+ unsigned short numDspBases = 8;
+ unsigned short numUartBases = 4;
+ unsigned short numDspIrqs = 5;
+ unsigned short numUartIrqs = 2;
+ unsigned short dspio_index = 0, uartio_index = 0;
+
+ PRINTK_5(TRACE_SMAPI,
+ "smapi::smapi_set_DSP_cfg entry mwave_3780i_irq %x mwave_3780i_io %x mwave_uart_irq %x mwave_uart_io %x\n",
+ mwave_3780i_irq, mwave_3780i_io, mwave_uart_irq, mwave_uart_io);
+
+ if (mwave_3780i_io) {
+ for (i = 0; i < numDspBases; i++) {
+ if (mwave_3780i_io == ausDspBases[i])
+ break;
+ }
+ if (i == numDspBases) {
+ PRINTK_ERROR(KERN_ERR_MWAVE "smapi::smapi_set_DSP_cfg: Error: Invalid mwave_3780i_io address %x. Aborting.\n", mwave_3780i_io);
+ return bRC;
+ }
+ dspio_index = i;
+ }
+
+ if (mwave_3780i_irq) {
+ for (i = 0; i < numDspIrqs; i++) {
+ if (mwave_3780i_irq == ausDspIrqs[i])
+ break;
+ }
+ if (i == numDspIrqs) {
+ PRINTK_ERROR(KERN_ERR_MWAVE "smapi::smapi_set_DSP_cfg: Error: Invalid mwave_3780i_irq %x. Aborting.\n", mwave_3780i_irq);
+ return bRC;
+ }
+ }
+
+ if (mwave_uart_io) {
+ for (i = 0; i < numUartBases; i++) {
+ if (mwave_uart_io == ausUartBases[i])
+ break;
+ }
+ if (i == numUartBases) {
+ PRINTK_ERROR(KERN_ERR_MWAVE "smapi::smapi_set_DSP_cfg: Error: Invalid mwave_uart_io address %x. Aborting.\n", mwave_uart_io);
+ return bRC;
+ }
+ uartio_index = i;
+ }
+
+
+ if (mwave_uart_irq) {
+ for (i = 0; i < numUartIrqs; i++) {
+ if (mwave_uart_irq == ausUartIrqs[i])
+ break;
+ }
+ if (i == numUartIrqs) {
+ PRINTK_ERROR(KERN_ERR_MWAVE "smapi::smapi_set_DSP_cfg: Error: Invalid mwave_uart_irq %x. Aborting.\n", mwave_uart_irq);
+ return bRC;
+ }
+ }
+
+ if (mwave_uart_irq || mwave_uart_io) {
+
+ /* Check serial port A */
+ bRC = smapi_request(0x1402, 0x0000, 0, 0,
+ &usAX, &usBX, &usCX, &usDX, &usDI, &usSI);
+ if (bRC) goto exit_smapi_request_error;
+ /* bRC == 0 */
+ if (usBX & 0x0100) { /* serial port A is present */
+ if (usCX & 1) { /* serial port is enabled */
+ if ((usSI & 0xFF) == mwave_uart_irq) {
+#ifndef MWAVE_FUTZ_WITH_OTHER_DEVICES
+ PRINTK_ERROR(KERN_ERR_MWAVE
+#else
+ PRINTK_3(TRACE_SMAPI,
+#endif
+ "smapi::smapi_set_DSP_cfg: Serial port A irq %x conflicts with mwave_uart_irq %x\n", usSI, mwave_uart_irq);
+#ifdef MWAVE_FUTZ_WITH_OTHER_DEVICES
+ PRINTK_1(TRACE_SMAPI,
+ "smapi::smapi_set_DSP_cfg Disabling conflicting serial port\n");
+ bRC = smapi_request(0x1403, 0x0100, 0, usSI,
+ &usAX, &usBX, &usCX, &usDX, &usDI, &usSI);
+ if (bRC) goto exit_smapi_request_error;
+ bRC = smapi_request(0x1402, 0x0000, 0, 0,
+ &usAX, &usBX, &usCX, &usDX, &usDI, &usSI);
+ if (bRC) goto exit_smapi_request_error;
+#else
+ goto exit_conflict;
+#endif
+ } else {
+ if ((usSI >> 8) == uartio_index) {
+#ifndef MWAVE_FUTZ_WITH_OTHER_DEVICES
+ PRINTK_ERROR(KERN_ERR_MWAVE
+#else
+ PRINTK_3(TRACE_SMAPI,
+#endif
+ "smapi::smapi_set_DSP_cfg: Serial port A base I/O address index %x conflicts with uartio_index %x\n", usSI >> 8, uartio_index);
+#ifdef MWAVE_FUTZ_WITH_OTHER_DEVICES
+ PRINTK_1(TRACE_SMAPI,
+ "smapi::smapi_set_DSP_cfg Disabling conflicting serial port\n");
+ bRC = smapi_request (0x1403, 0x0100, 0, usSI,
+ &usAX, &usBX, &usCX, &usDX, &usDI, &usSI);
+ if (bRC) goto exit_smapi_request_error;
+ bRC = smapi_request (0x1402, 0x0000, 0, 0,
+ &usAX, &usBX, &usCX, &usDX, &usDI, &usSI);
+ if (bRC) goto exit_smapi_request_error;
+#else
+ goto exit_conflict;
+#endif
+ }
+ }
+ }
+ }
+
+ /* Check serial port B */
+ bRC = smapi_request(0x1404, 0x0000, 0, 0,
+ &usAX, &usBX, &usCX, &usDX, &usDI, &usSI);
+ if (bRC) goto exit_smapi_request_error;
+ /* bRC == 0 */
+ if (usBX & 0x0100) { /* serial port B is present */
+ if (usCX & 1) { /* serial port is enabled */
+ if ((usSI & 0xFF) == mwave_uart_irq) {
+#ifndef MWAVE_FUTZ_WITH_OTHER_DEVICES
+ PRINTK_ERROR(KERN_ERR_MWAVE
+#else
+ PRINTK_3(TRACE_SMAPI,
+#endif
+ "smapi::smapi_set_DSP_cfg: Serial port B irq %x conflicts with mwave_uart_irq %x\n", usSI, mwave_uart_irq);
+#ifdef MWAVE_FUTZ_WITH_OTHER_DEVICES
+ PRINTK_1(TRACE_SMAPI,
+ "smapi::smapi_set_DSP_cfg Disabling conflicting serial port\n");
+ bRC = smapi_request(0x1405, 0x0100, 0, usSI,
+ &usAX, &usBX, &usCX, &usDX, &usDI, &usSI);
+ if (bRC) goto exit_smapi_request_error;
+ bRC = smapi_request(0x1404, 0x0000, 0, 0,
+ &usAX, &usBX, &usCX, &usDX, &usDI, &usSI);
+ if (bRC) goto exit_smapi_request_error;
+#else
+ goto exit_conflict;
+#endif
+ } else {
+ if ((usSI >> 8) == uartio_index) {
+#ifndef MWAVE_FUTZ_WITH_OTHER_DEVICES
+ PRINTK_ERROR(KERN_ERR_MWAVE
+#else
+ PRINTK_3(TRACE_SMAPI,
+#endif
+ "smapi::smapi_set_DSP_cfg: Serial port B base I/O address index %x conflicts with uartio_index %x\n", usSI >> 8, uartio_index);
+#ifdef MWAVE_FUTZ_WITH_OTHER_DEVICES
+ PRINTK_1 (TRACE_SMAPI,
+ "smapi::smapi_set_DSP_cfg Disabling conflicting serial port\n");
+ bRC = smapi_request (0x1405, 0x0100, 0, usSI,
+ &usAX, &usBX, &usCX, &usDX, &usDI, &usSI);
+ if (bRC) goto exit_smapi_request_error;
+ bRC = smapi_request (0x1404, 0x0000, 0, 0,
+ &usAX, &usBX, &usCX, &usDX, &usDI, &usSI);
+ if (bRC) goto exit_smapi_request_error;
+#else
+ goto exit_conflict;
+#endif
+ }
+ }
+ }
+ }
+
+ /* Check IR port */
+ bRC = smapi_request(0x1700, 0x0000, 0, 0,
+ &usAX, &usBX, &usCX, &usDX, &usDI, &usSI);
+ if (bRC) goto exit_smapi_request_error;
+ bRC = smapi_request(0x1704, 0x0000, 0, 0,
+ &usAX, &usBX, &usCX, &usDX, &usDI, &usSI);
+ if (bRC) goto exit_smapi_request_error;
+ /* bRC == 0 */
+ if ((usCX & 0xff) == mwave_uart_irq) { /* serial port is enabled */
+#ifndef MWAVE_FUTZ_WITH_OTHER_DEVICES
+ PRINTK_ERROR(KERN_ERR_MWAVE
+#else
+ PRINTK_3(TRACE_SMAPI,
+#endif
+ "smapi::smapi_set_DSP_cfg: IR port irq %x conflicts with mwave_uart_irq %x\n", usSI, mwave_uart_irq);
+#ifdef MWAVE_FUTZ_WITH_OTHER_DEVICES
+ PRINTK_1(TRACE_SMAPI,
+ "smapi::smapi_set_DSP_cfg Disabling conflicting IR port\n");
+ bRC = smapi_request(0x1701, 0x0100, 0, 0,
+ &usAX, &usBX, &usCX, &usDX, &usDI, &usSI);
+ if (bRC) goto exit_smapi_request_error;
+ bRC = smapi_request(0x1700, 0, 0, 0,
+ &usAX, &usBX, &usCX, &usDX, &usDI, &usSI);
+ if (bRC) goto exit_smapi_request_error;
+ bRC = smapi_request(0x1705, 0x01ff, 0, usSI,
+ &usAX, &usBX, &usCX, &usDX, &usDI, &usSI);
+ if (bRC) goto exit_smapi_request_error;
+ bRC = smapi_request(0x1704, 0x0000, 0, 0,
+ &usAX, &usBX, &usCX, &usDX, &usDI, &usSI);
+ if (bRC) goto exit_smapi_request_error;
+#else
+ goto exit_conflict;
+#endif
+ } else {
+ if ((usSI & 0xff) == uartio_index) {
+#ifndef MWAVE_FUTZ_WITH_OTHER_DEVICES
+ PRINTK_ERROR(KERN_ERR_MWAVE
+#else
+ PRINTK_3(TRACE_SMAPI,
+#endif
+ "smapi::smapi_set_DSP_cfg: IR port base I/O address index %x conflicts with uartio_index %x\n", usSI & 0xff, uartio_index);
+#ifdef MWAVE_FUTZ_WITH_OTHER_DEVICES
+ PRINTK_1(TRACE_SMAPI,
+ "smapi::smapi_set_DSP_cfg Disabling conflicting IR port\n");
+ bRC = smapi_request(0x1701, 0x0100, 0, 0,
+ &usAX, &usBX, &usCX, &usDX, &usDI, &usSI);
+ if (bRC) goto exit_smapi_request_error;
+ bRC = smapi_request(0x1700, 0, 0, 0,
+ &usAX, &usBX, &usCX, &usDX, &usDI, &usSI);
+ if (bRC) goto exit_smapi_request_error;
+ bRC = smapi_request(0x1705, 0x01ff, 0, usSI,
+ &usAX, &usBX, &usCX, &usDX, &usDI, &usSI);
+ if (bRC) goto exit_smapi_request_error;
+ bRC = smapi_request(0x1704, 0x0000, 0, 0,
+ &usAX, &usBX, &usCX, &usDX, &usDI, &usSI);
+ if (bRC) goto exit_smapi_request_error;
+#else
+ goto exit_conflict;
+#endif
+ }
+ }
+ }
+
+ bRC = smapi_request(0x1802, 0x0000, 0, 0,
SHAR_EOF
true || echo 'restore of patch-2.4.11 failed'
fi
echo 'End of part 07'
echo 'File patch-2.4.11 is continued in part 08'
echo "08" > _shar_seq_.tmp
exit 0