DAVIS240C interface with FPGA

[jonah.s...@gmail.com]

Hi all, 

I am hoping to develop hardware interfaces to the event-based cameras and am looking to use existing COTS sensors as prototype master devices. I saw that this can be achieved using a DAVIS240C by interfacing with the CPLD in jAER, (https://gitlab.com/inivation/inivation-docs/-/blob/master/Hardware%20user%20guides/User_guide_-_DAVIS240.md#receiving-address-events-directly-from-the-chip). I had a couple follow up questions:

1. In general, we can use the mentioned SAMTEC cable to interface the DAVIS with an FPGA. However, in the case of the given example with jAER and cAER here (https://gitlab.com/inivation/dv/libcaer/blob/master/examples/davis_enable_aer.cpp), it seems that the PC is responsible for configuring biases and other chip parameters so is the FPGA solely responsible for the BD-AER handshaking?

2. Is there a comparable means to configure the camera within DV platform?

3. Are there any other available models that allow for external AER control?

Any help is greatly appreciated!

Jonah

[Luca Longinotti]

Hello Jonah,

1. Correct. There's no support for sending biases and other
configuration over that cable, only for taking over the AER handshake.

2. Yes, the libcaer example pretty much stays the same, and the 'AER
enable external' configuration option is also available in DV's Capture
module full configuration. So the same steps apply.

3. No.

Hope this helps, have a great week!

--
Luca Longinotti (llongi)

Software Engineer
iniVation AG - https://inivation.com/
Zurich, Switzerland
Office: +41 44 500 32 14

Support - https://inivation.com/support/

[jonah.s...@gmail.com]

Hi Luca - 

Two follow-up questions to our prior discussion above:

1. On the hardware guide (Hardware user guides/User_guide_-_DAVIS240.md · master · iniVation AG / inivation-docs · GitLab), you mention that AERMonAdd6 and 7 are inverted on the DAVIS240C. Do you mean that they are active low or rather their positions are flipped?

2. When handshaking externally using the provided connector, the external FPGA or uC does not need to drive any other signals except pin 39, nAckChip. Is that correct? 

Any help is greatly appreciated!

Jonah

[Luca Longinotti]

Hello Jonah,

1) Their positions are flipped.

2) Correct, nACK is the only signal required to be driven.

Hope this helps, have a nice week!

-- 

Luca Longinotti (llongi)

Head of Embedded Platforms
iniVation AG - https://inivation.com/

Zurich, Switzerland
Office: +41 44 500 32 14