DAVIS internal capacitance

[Alessandra Colucci]

Dear all,

I'm working on some experimental simulation with a DVS model. It is possible to know (if you know) the internal parasitic capacitance (Cfb, Cpd, etc.) and transistor early voltage values of a DAVIS?

Thank you.

Regards,

Alessandra Colucci

[Tobi Delbruck (INI)]

Hi Alessandra, Thanks for asking. We get those numbers via
back-annotated 3D parasitic plus FET model parameters, usually only
implicitly during the SPICE simulations.  I'm not sure how much we can
really trust the absolute values either since the foundries may or may
not do a good job to characterize them in their PDKs.

As round numbers, you can take e.g. 0.1fF/um of drain/source edges for
the FETs. If you have the SPICE parameter that number is buried in the
there via the BSIM4 (or whatever) model.

And in (very) round numbers, about V_e=10V/um channel length for the
typical FETs. The problem is that very short FETs have much smaller V_e
because of the intercept with zero V_e a bit below the min FET length.

But are you asking about the designed capacitance values?  i.e. for the
MIM caps, the designed value? Or about all parasitics?

Sorry for the complicated and cryptic answer.

I can look up the DAVIS pixel schematic and give more precise values if
needed.