DAVIS346 AER interface with FPGA

[琦彬李]

1.Are there any cases for DAVIS346 AER on FPGA?

2.We want to use DAVIS346 AER to connect directly to the FPGA, is there a timing specification or verilog simulation code?  

[Luca Longinotti]

1. The device is shipped with a case, see the manual for a picture. The FPGA part and its possible case and connectors are up to the customer.

2. There is a VHDL state machine example, as well as all the protocol detail in the manual here:

https://docs.inivation.com/hardware/current-products/davis346-aer.html#fpga-receiver-state-machine

No timing specification as AER is an asynchronous bus without clocks.

-- 

Luca Longinotti (llongi)

Head of Embedded Platforms
iniVation AG - https://inivation.com/
Zurich, Switzerland
Office: +41 44 500 32 14