Results of the CAESAR Round 3 Hardware Benchmarking

[Kris Gaj]

Dear All,

A comprehensive presentation, entitled

  Benchmarking of Round 3 CAESAR Candidates in Hardware: Methodology, Designs & Results,

has been posted at

  https://cryptography.gmu.edu/athena/index.php?id=CAESAR

The direct link is:

  https://cryptography.gmu.edu/athena/presentations/CAESAR_R3_HW_Benchmarking.pdf

This presentation covers

  * A brief overview of the CAESAR HW API and the development of implementations compliant with this API

  * Overview of VHDL/Verilog code of Round 3 candidates

  * Discussion of Use Cases

  * Our detailed benchmarking methodology

  * Graphical representation of results,

    including 

    - two-dimensional graphs Throughput vs. Area, as well as the 

    - relative speed-up, area reduction, and efficiency improvement compared to AES-GCM

  * Hints on an effective use of the ATHENa database of results

  * Conclusions.

  

All designs of Round 3 candidates are comprehensively summarized in the following two tables

  https://cryptography.gmu.edu/athena/CAESAR_HW_Summary_1.html 

  https://cryptography.gmu.edu/athena/CAESAR_HW_Summary_2.html

  

Additionally, we encourage everybody to vist our on-line database results, available at

  https://cryptography.gmu.edu/athenadb/fpga_auth_cipher/rankings_view  

For FOUR major rankings, please choose

  

Family:

 Virtex 6 (default)

 Virtex 7

 Stratix IV

 Stratix V.

After each change to the options, please make sure to click on the 

  Update 

button, located at the bottom of the Result Filtering area, just above the table with results.

If you want to return to the default settings, please click on

  FPGA Rankings,

in the menu located on the left side of the page.

For Use Cases 2 & 3, we recommend as the Primary Evaluation Criteria: 

  * Throughput/Area (demonstrating the best balance between speed and area), followed by

  * Throughput (demonstrating the best speed alone).

     

For Use Case 1, we recommend as the Primary Evaluation Criteria: 

  * Area (demonstrating low cost of the implementation), followed by

  * Throughput/Area (demonstrating the best balance between speed and area).

You can switch among these Evaluation Criteria, by using the option

Ranking:

  [X] Throughput/Area 

  [  ] Throughput   

  [  ] Area            

The results for four additional designs 

   CLOC-TWINE, SILC-LED, SILC-PRESENT (from the CLOC-SILC Team), and

   JAMBU-SIMON (a revised version from CCRG NTU Singapore) 

are not available yet, due to the incompatibility of the received code with our 

FPGA tools (CLOC/SILC) and a very recent submission (JAMBU).

If the benchmarking of these implementations is successful, we will add the obtained

results to the database and to the presentation within the next few days.

For the one stop page with links to all the aforementioned resources (and many more),

please visit:

   https://cryptography.gmu.edu/athena/index.php?id=CAESAR 

Any comments, questions, and suggestions for the modifications & extensions are very welcome!

Regards,

Kris

on behalf of the GMU Benchmarking Team

https://cryptography.gmu.edu/athena

https://cryptography.gmu.edu

http://ece.gmu.edu/~kgaj